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63ef5d8c28
CMD23 causes lots of errors in kernel on some freescale SoCs (P1020, P1021, P1022, P1024, P1025 and P4080) when MMC card used, which is because these controllers does not support CMD23, even on the SoCs which declares CMD23 is supported. Therefore, we'll not use CMD23. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>
245 lines
6.6 KiB
C
245 lines
6.6 KiB
C
/*
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* Freescale eSDHC controller driver.
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*
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* Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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#define VENDOR_V_22 0x12
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static u32 esdhc_readl(struct sdhci_host *host, int reg)
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{
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u32 ret;
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ret = in_be32(host->ioaddr + reg);
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/*
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* The bit of ADMA flag in eSDHC is not compatible with standard
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* SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
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* supported by eSDHC.
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* And for many FSL eSDHC controller, the reset value of field
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* SDHCI_CAN_DO_ADMA1 is one, but some of them can't support ADMA,
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* only these vendor version is greater than 2.2/0x12 support ADMA.
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* For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
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* the verdor version number, oxFE is SDHCI_HOST_VERSION.
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*/
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if ((reg == SDHCI_CAPABILITIES) && (ret & SDHCI_CAN_DO_ADMA1)) {
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u32 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
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tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
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if (tmp > VENDOR_V_22)
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ret |= SDHCI_CAN_DO_ADMA2;
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}
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return ret;
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}
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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int base = reg & ~0x3;
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int shift = (reg & 0x2) * 8;
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if (unlikely(reg == SDHCI_HOST_VERSION))
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ret = in_be32(host->ioaddr + base) & 0xffff;
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else
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ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
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return ret;
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}
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static u8 esdhc_readb(struct sdhci_host *host, int reg)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
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/*
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* "DMA select" locates at offset 0x28 in SD specification, but on
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* P5020 or P3041, it locates at 0x29.
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*/
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if (reg == SDHCI_HOST_CONTROL) {
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u32 dma_bits;
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dma_bits = in_be32(host->ioaddr + reg);
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
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/* fixup the result */
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ret &= ~SDHCI_CTRL_DMA_MASK;
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ret |= dma_bits;
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}
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return ret;
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}
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static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (reg == SDHCI_BLOCK_SIZE) {
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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}
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sdhci_be32bs_writew(host, val, reg);
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}
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static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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/*
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* "DMA select" location is offset 0x28 in SD specification, but on
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* P5020 or P3041, it's located at 0x29.
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*/
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if (reg == SDHCI_HOST_CONTROL) {
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u32 dma_bits;
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
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clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
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dma_bits);
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val &= ~SDHCI_CTRL_DMA_MASK;
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val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
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}
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
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if (reg == SDHCI_HOST_CONTROL)
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val &= ~ESDHC_HOST_CONTROL_RES;
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sdhci_be32bs_writeb(host, val, reg);
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}
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static int esdhc_of_enable_dma(struct sdhci_host *host)
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{
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setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
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return 0;
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}
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static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return pltfm_host->clock;
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}
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static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return pltfm_host->clock / 256 / 16;
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}
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static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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/* Workaround to reduce the clock frequency for p1010 esdhc */
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if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
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if (clock > 20000000)
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clock -= 5000000;
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if (clock > 40000000)
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clock -= 5000000;
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}
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/* Set the clock */
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esdhc_set_clock(host, clock);
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}
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#ifdef CONFIG_PM
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static u32 esdhc_proctl;
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static void esdhc_of_suspend(struct sdhci_host *host)
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{
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esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
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}
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static void esdhc_of_resume(struct sdhci_host *host)
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{
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esdhc_of_enable_dma(host);
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sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
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}
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#endif
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static void esdhc_of_platform_init(struct sdhci_host *host)
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{
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u32 vvn;
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vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
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vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
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if (vvn == VENDOR_V_22)
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host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
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}
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static struct sdhci_ops sdhci_esdhc_ops = {
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.read_l = esdhc_readl,
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.read_w = esdhc_readw,
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.read_b = esdhc_readb,
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.write_l = sdhci_be32bs_writel,
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.write_w = esdhc_writew,
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.write_b = esdhc_writeb,
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.set_clock = esdhc_of_set_clock,
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.enable_dma = esdhc_of_enable_dma,
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.get_max_clock = esdhc_of_get_max_clock,
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.get_min_clock = esdhc_of_get_min_clock,
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.platform_init = esdhc_of_platform_init,
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#ifdef CONFIG_PM
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.platform_suspend = esdhc_of_suspend,
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.platform_resume = esdhc_of_resume,
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#endif
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};
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static struct sdhci_pltfm_data sdhci_esdhc_pdata = {
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/*
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* card detection could be handled via GPIO
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* eSDHC cannot support End Attribute in NOP ADMA descriptor
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*/
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.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
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| SDHCI_QUIRK_NO_CARD_NO_RESET
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| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.ops = &sdhci_esdhc_ops,
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};
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static int __devinit sdhci_esdhc_probe(struct platform_device *pdev)
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{
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return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
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}
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static int __devexit sdhci_esdhc_remove(struct platform_device *pdev)
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{
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return sdhci_pltfm_unregister(pdev);
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}
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static const struct of_device_id sdhci_esdhc_of_match[] = {
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{ .compatible = "fsl,mpc8379-esdhc" },
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{ .compatible = "fsl,mpc8536-esdhc" },
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{ .compatible = "fsl,esdhc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
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static struct platform_driver sdhci_esdhc_driver = {
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.driver = {
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.name = "sdhci-esdhc",
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.owner = THIS_MODULE,
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.of_match_table = sdhci_esdhc_of_match,
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.pm = SDHCI_PLTFM_PMOPS,
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},
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.probe = sdhci_esdhc_probe,
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.remove = __devexit_p(sdhci_esdhc_remove),
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};
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module_platform_driver(sdhci_esdhc_driver);
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MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
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MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
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"Anton Vorontsov <avorontsov@ru.mvista.com>");
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MODULE_LICENSE("GPL v2");
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