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83a77e9ec4
There are hardware PCI implementations of Cadence GEM network controller. This patch will allow to use such hardware with reuse of existing Platform Driver. Signed-off-by: Bartosz Folta <bfolta@cadence.com> Signed-off-by: David S. Miller <davem@davemloft.net>
32 lines
799 B
C
32 lines
799 B
C
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MACB_PDATA_H__
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#define __MACB_PDATA_H__
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#include <linux/clk.h>
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/**
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* struct macb_platform_data - platform data for MACB Ethernet
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* @phy_mask: phy mask passed when register the MDIO bus
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* within the driver
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* @phy_irq_pin: PHY IRQ
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* @is_rmii: using RMII interface?
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* @rev_eth_addr: reverse Ethernet address byte order
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* @pclk: platform clock
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* @hclk: AHB clock
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*/
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struct macb_platform_data {
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u32 phy_mask;
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int phy_irq_pin;
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u8 is_rmii;
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u8 rev_eth_addr;
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struct clk *pclk;
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struct clk *hclk;
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};
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#endif /* __MACB_PDATA_H__ */
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