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726fef09b8
The AB8540 was an evolved version of the AB8500, but it was never mass produced or put into products, only reference designs exist. The upstream support was never completed and it is unlikely that this will happen so drop the support for now to simplify maintenance of the AB8500. Cc: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
/*
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* abx500 clock implementation for ux500 platform.
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*
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* Copyright (C) 2012 ST-Ericsson SA
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* Author: Ulf Hansson <ulf.hansson@linaro.org>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/abx500/ab8500.h>
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#include <linux/mfd/abx500/ab8500-sysctrl.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <dt-bindings/clock/ste-ab8500.h>
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#include "clk.h"
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#define AB8500_NUM_CLKS 6
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static struct clk *ab8500_clks[AB8500_NUM_CLKS];
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static struct clk_onecell_data ab8500_clk_data;
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/* Clock definitions for ab8500 */
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static int ab8500_reg_clks(struct device *dev)
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{
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int ret;
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struct clk *clk;
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struct device_node *np = dev->of_node;
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const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
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u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
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u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
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u8 intclk_reg_bits[] = {
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0 ,
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(1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
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};
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/* Enable SWAT */
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ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
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if (ret)
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return ret;
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/* ab8500_sysclk2 */
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clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
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AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
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ab8500_clks[AB8500_SYSCLK_BUF2] = clk;
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/* ab8500_sysclk3 */
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clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
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AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
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ab8500_clks[AB8500_SYSCLK_BUF3] = clk;
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/* ab8500_sysclk4 */
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clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
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AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
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ab8500_clks[AB8500_SYSCLK_BUF4] = clk;
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/* ab_ulpclk */
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clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
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AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
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38400000, 9000, 0);
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ab8500_clks[AB8500_SYSCLK_ULP] = clk;
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/* ab8500_intclk */
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clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
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intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
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ab8500_clks[AB8500_SYSCLK_INT] = clk;
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/* ab8500_audioclk */
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clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
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AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
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ab8500_clks[AB8500_SYSCLK_AUDIO] = clk;
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ab8500_clk_data.clks = ab8500_clks;
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ab8500_clk_data.clk_num = ARRAY_SIZE(ab8500_clks);
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of_clk_add_provider(np, of_clk_src_onecell_get, &ab8500_clk_data);
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dev_info(dev, "registered clocks for ab850x\n");
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return 0;
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}
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static int abx500_clk_probe(struct platform_device *pdev)
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{
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struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent);
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int ret;
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if (is_ab8500(parent) || is_ab8505(parent)) {
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ret = ab8500_reg_clks(&pdev->dev);
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} else {
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dev_err(&pdev->dev, "non supported plf id\n");
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return -ENODEV;
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}
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return ret;
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}
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static const struct of_device_id abx500_clk_match[] = {
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{ .compatible = "stericsson,ab8500-clk", },
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{}
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};
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static struct platform_driver abx500_clk_driver = {
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.driver = {
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.name = "abx500-clk",
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.of_match_table = abx500_clk_match,
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},
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.probe = abx500_clk_probe,
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};
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static int __init abx500_clk_init(void)
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{
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return platform_driver_register(&abx500_clk_driver);
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}
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arch_initcall(abx500_clk_init);
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MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
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MODULE_DESCRIPTION("ABX500 clk driver");
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MODULE_LICENSE("GPL v2");
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