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![Daniel Lezcano](/assets/img/avatar_default.png)
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
259 lines
7 KiB
C
259 lines
7 KiB
C
/*
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* at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
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*
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* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
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* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
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* Converted to ClockSource/ClockEvents by David Brownell.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "AT91: PIT: " fmt
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#define AT91_PIT_MR 0x00 /* Mode Register */
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#define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
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#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
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#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */
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#define AT91_PIT_SR 0x04 /* Status Register */
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#define AT91_PIT_PITS BIT(0) /* Timer Status */
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#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
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#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
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#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */
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#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */
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#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
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#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
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struct pit_data {
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struct clock_event_device clkevt;
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struct clocksource clksrc;
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void __iomem *base;
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u32 cycle;
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u32 cnt;
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unsigned int irq;
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struct clk *mck;
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};
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static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
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{
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return container_of(clksrc, struct pit_data, clksrc);
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}
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static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt)
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{
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return container_of(clkevt, struct pit_data, clkevt);
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}
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static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
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{
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return readl_relaxed(base + reg_offset);
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}
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static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
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{
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writel_relaxed(value, base + reg_offset);
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}
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/*
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* Clocksource: just a monotonic counter of MCK/16 cycles.
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* We don't care whether or not PIT irqs are enabled.
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*/
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static u64 read_pit_clk(struct clocksource *cs)
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{
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struct pit_data *data = clksrc_to_pit_data(cs);
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unsigned long flags;
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u32 elapsed;
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u32 t;
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raw_local_irq_save(flags);
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elapsed = data->cnt;
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t = pit_read(data->base, AT91_PIT_PIIR);
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raw_local_irq_restore(flags);
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elapsed += PIT_PICNT(t) * data->cycle;
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elapsed += PIT_CPIV(t);
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return elapsed;
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}
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static int pit_clkevt_shutdown(struct clock_event_device *dev)
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{
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struct pit_data *data = clkevt_to_pit_data(dev);
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/* disable irq, leaving the clocksource active */
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pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN);
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return 0;
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}
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/*
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* Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
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*/
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static int pit_clkevt_set_periodic(struct clock_event_device *dev)
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{
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struct pit_data *data = clkevt_to_pit_data(dev);
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/* update clocksource counter */
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data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
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pit_write(data->base, AT91_PIT_MR,
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(data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);
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return 0;
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}
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static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
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{
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struct pit_data *data = clkevt_to_pit_data(cedev);
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/* Disable timer */
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pit_write(data->base, AT91_PIT_MR, 0);
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}
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static void at91sam926x_pit_reset(struct pit_data *data)
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{
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/* Disable timer and irqs */
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pit_write(data->base, AT91_PIT_MR, 0);
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/* Clear any pending interrupts, wait for PIT to stop counting */
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while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
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cpu_relax();
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/* Start PIT but don't enable IRQ */
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pit_write(data->base, AT91_PIT_MR,
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(data->cycle - 1) | AT91_PIT_PITEN);
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}
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static void at91sam926x_pit_resume(struct clock_event_device *cedev)
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{
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struct pit_data *data = clkevt_to_pit_data(cedev);
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at91sam926x_pit_reset(data);
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}
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
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{
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struct pit_data *data = dev_id;
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/* The PIT interrupt may be disabled, and is shared */
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if (clockevent_state_periodic(&data->clkevt) &&
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(pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
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/* Get number of ticks performed before irq, and ack it */
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data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,
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AT91_PIT_PIVR));
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data->clkevt.event_handler(&data->clkevt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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/*
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* Set up both clocksource and clockevent support.
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*/
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static int __init at91sam926x_pit_dt_init(struct device_node *node)
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{
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unsigned long pit_rate;
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unsigned bits;
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int ret;
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struct pit_data *data;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->base = of_iomap(node, 0);
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if (!data->base) {
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pr_err("Could not map PIT address\n");
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return -ENXIO;
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}
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data->mck = of_clk_get(node, 0);
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if (IS_ERR(data->mck)) {
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pr_err("Unable to get mck clk\n");
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return PTR_ERR(data->mck);
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}
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ret = clk_prepare_enable(data->mck);
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if (ret) {
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pr_err("Unable to enable mck\n");
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return ret;
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}
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/* Get the interrupts property */
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data->irq = irq_of_parse_and_map(node, 0);
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if (!data->irq) {
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pr_err("Unable to get IRQ from DT\n");
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return -EINVAL;
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}
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/*
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* Use our actual MCK to figure out how many MCK/16 ticks per
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* 1/HZ period (instead of a compile-time constant LATCH).
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*/
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pit_rate = clk_get_rate(data->mck) / 16;
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data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
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WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);
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/* Initialize and enable the timer */
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at91sam926x_pit_reset(data);
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/*
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* Register clocksource. The high order bits of PIV are unused,
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* so this isn't a 32-bit counter unless we get clockevent irqs.
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*/
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bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;
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data->clksrc.mask = CLOCKSOURCE_MASK(bits);
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data->clksrc.name = "pit";
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data->clksrc.rating = 175;
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data->clksrc.read = read_pit_clk;
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data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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ret = clocksource_register_hz(&data->clksrc, pit_rate);
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if (ret) {
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pr_err("Failed to register clocksource\n");
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return ret;
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}
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/* Set up irq handler */
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ret = request_irq(data->irq, at91sam926x_pit_interrupt,
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IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
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"at91_tick", data);
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if (ret) {
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pr_err("Unable to setup IRQ\n");
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return ret;
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}
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/* Set up and register clockevents */
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data->clkevt.name = "pit";
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data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
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data->clkevt.shift = 32;
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data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
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data->clkevt.rating = 100;
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data->clkevt.cpumask = cpumask_of(0);
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data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
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data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
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data->clkevt.resume = at91sam926x_pit_resume;
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data->clkevt.suspend = at91sam926x_pit_suspend;
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clockevents_register_device(&data->clkevt);
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return 0;
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}
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TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
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at91sam926x_pit_dt_init);
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