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![Gustavo A. R. Silva](/assets/img/avatar_default.png)
Print and propagate the return value of platform_get_irq on failure. Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
767 lines
19 KiB
C
767 lines
19 KiB
C
/*
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* Copyright (C) 2016 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
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*
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* The driver is based on information gathered from
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* drivers/mxc/security/mxc_scc.c which can be found in
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* the Freescale linux-2.6-imx.git in the imx_2.6.35_maintain branch.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/crypto.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <crypto/algapi.h>
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#include <crypto/des.h>
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/* Secure Memory (SCM) registers */
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#define SCC_SCM_RED_START 0x0000
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#define SCC_SCM_BLACK_START 0x0004
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#define SCC_SCM_LENGTH 0x0008
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#define SCC_SCM_CTRL 0x000C
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#define SCC_SCM_STATUS 0x0010
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#define SCC_SCM_ERROR_STATUS 0x0014
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#define SCC_SCM_INTR_CTRL 0x0018
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#define SCC_SCM_CFG 0x001C
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#define SCC_SCM_INIT_VECTOR_0 0x0020
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#define SCC_SCM_INIT_VECTOR_1 0x0024
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#define SCC_SCM_RED_MEMORY 0x0400
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#define SCC_SCM_BLACK_MEMORY 0x0800
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/* Security Monitor (SMN) Registers */
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#define SCC_SMN_STATUS 0x1000
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#define SCC_SMN_COMMAND 0x1004
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#define SCC_SMN_SEQ_START 0x1008
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#define SCC_SMN_SEQ_END 0x100C
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#define SCC_SMN_SEQ_CHECK 0x1010
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#define SCC_SMN_BIT_COUNT 0x1014
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#define SCC_SMN_BITBANK_INC_SIZE 0x1018
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#define SCC_SMN_BITBANK_DECREMENT 0x101C
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#define SCC_SMN_COMPARE_SIZE 0x1020
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#define SCC_SMN_PLAINTEXT_CHECK 0x1024
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#define SCC_SMN_CIPHERTEXT_CHECK 0x1028
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#define SCC_SMN_TIMER_IV 0x102C
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#define SCC_SMN_TIMER_CONTROL 0x1030
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#define SCC_SMN_DEBUG_DETECT_STAT 0x1034
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#define SCC_SMN_TIMER 0x1038
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#define SCC_SCM_CTRL_START_CIPHER BIT(2)
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#define SCC_SCM_CTRL_CBC_MODE BIT(1)
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#define SCC_SCM_CTRL_DECRYPT_MODE BIT(0)
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#define SCC_SCM_STATUS_LEN_ERR BIT(12)
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#define SCC_SCM_STATUS_SMN_UNBLOCKED BIT(11)
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#define SCC_SCM_STATUS_CIPHERING_DONE BIT(10)
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#define SCC_SCM_STATUS_ZEROIZING_DONE BIT(9)
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#define SCC_SCM_STATUS_INTR_STATUS BIT(8)
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#define SCC_SCM_STATUS_SEC_KEY BIT(7)
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#define SCC_SCM_STATUS_INTERNAL_ERR BIT(6)
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#define SCC_SCM_STATUS_BAD_SEC_KEY BIT(5)
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#define SCC_SCM_STATUS_ZEROIZE_FAIL BIT(4)
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#define SCC_SCM_STATUS_SMN_BLOCKED BIT(3)
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#define SCC_SCM_STATUS_CIPHERING BIT(2)
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#define SCC_SCM_STATUS_ZEROIZING BIT(1)
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#define SCC_SCM_STATUS_BUSY BIT(0)
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#define SCC_SMN_STATUS_STATE_MASK 0x0000001F
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#define SCC_SMN_STATE_START 0x0
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/* The SMN is zeroizing its RAM during reset */
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#define SCC_SMN_STATE_ZEROIZE_RAM 0x5
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/* SMN has passed internal checks */
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#define SCC_SMN_STATE_HEALTH_CHECK 0x6
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/* Fatal Security Violation. SMN is locked, SCM is inoperative. */
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#define SCC_SMN_STATE_FAIL 0x9
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/* SCC is in secure state. SCM is using secret key. */
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#define SCC_SMN_STATE_SECURE 0xA
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/* SCC is not secure. SCM is using default key. */
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#define SCC_SMN_STATE_NON_SECURE 0xC
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#define SCC_SCM_INTR_CTRL_ZEROIZE_MEM BIT(2)
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#define SCC_SCM_INTR_CTRL_CLR_INTR BIT(1)
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#define SCC_SCM_INTR_CTRL_MASK_INTR BIT(0)
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/* Size, in blocks, of Red memory. */
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#define SCC_SCM_CFG_BLACK_SIZE_MASK 0x07fe0000
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#define SCC_SCM_CFG_BLACK_SIZE_SHIFT 17
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/* Size, in blocks, of Black memory. */
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#define SCC_SCM_CFG_RED_SIZE_MASK 0x0001ff80
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#define SCC_SCM_CFG_RED_SIZE_SHIFT 7
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/* Number of bytes per block. */
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#define SCC_SCM_CFG_BLOCK_SIZE_MASK 0x0000007f
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#define SCC_SMN_COMMAND_TAMPER_LOCK BIT(4)
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#define SCC_SMN_COMMAND_CLR_INTR BIT(3)
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#define SCC_SMN_COMMAND_CLR_BIT_BANK BIT(2)
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#define SCC_SMN_COMMAND_EN_INTR BIT(1)
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#define SCC_SMN_COMMAND_SET_SOFTWARE_ALARM BIT(0)
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#define SCC_KEY_SLOTS 20
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#define SCC_MAX_KEY_SIZE 32
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#define SCC_KEY_SLOT_SIZE 32
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#define SCC_CRC_CCITT_START 0xFFFF
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/*
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* Offset into each RAM of the base of the area which is not
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* used for Stored Keys.
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*/
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#define SCC_NON_RESERVED_OFFSET (SCC_KEY_SLOTS * SCC_KEY_SLOT_SIZE)
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/* Fixed padding for appending to plaintext to fill out a block */
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static char scc_block_padding[8] = { 0x80, 0, 0, 0, 0, 0, 0, 0 };
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enum mxc_scc_state {
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SCC_STATE_OK,
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SCC_STATE_UNIMPLEMENTED,
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SCC_STATE_FAILED
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};
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struct mxc_scc {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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bool hw_busy;
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spinlock_t lock;
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struct crypto_queue queue;
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struct crypto_async_request *req;
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int block_size_bytes;
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int black_ram_size_blocks;
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int memory_size_bytes;
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int bytes_remaining;
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void __iomem *red_memory;
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void __iomem *black_memory;
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};
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struct mxc_scc_ctx {
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struct mxc_scc *scc;
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struct scatterlist *sg_src;
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size_t src_nents;
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struct scatterlist *sg_dst;
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size_t dst_nents;
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unsigned int offset;
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unsigned int size;
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unsigned int ctrl;
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};
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struct mxc_scc_crypto_tmpl {
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struct mxc_scc *scc;
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struct crypto_alg alg;
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};
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static int mxc_scc_get_data(struct mxc_scc_ctx *ctx,
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struct crypto_async_request *req)
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{
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struct ablkcipher_request *ablkreq = ablkcipher_request_cast(req);
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struct mxc_scc *scc = ctx->scc;
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size_t len;
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void __iomem *from;
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if (ctx->ctrl & SCC_SCM_CTRL_DECRYPT_MODE)
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from = scc->red_memory;
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else
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from = scc->black_memory;
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dev_dbg(scc->dev, "pcopy: from 0x%p %d bytes\n", from,
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ctx->dst_nents * 8);
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len = sg_pcopy_from_buffer(ablkreq->dst, ctx->dst_nents,
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from, ctx->size, ctx->offset);
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if (!len) {
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dev_err(scc->dev, "pcopy err from 0x%p (len=%d)\n", from, len);
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return -EINVAL;
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR,
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"red memory@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4,
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scc->red_memory, ctx->size, 1);
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print_hex_dump(KERN_ERR,
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"black memory@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4,
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scc->black_memory, ctx->size, 1);
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#endif
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ctx->offset += len;
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if (ctx->offset < ablkreq->nbytes)
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return -EINPROGRESS;
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return 0;
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}
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static int mxc_scc_ablkcipher_req_init(struct ablkcipher_request *req,
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struct mxc_scc_ctx *ctx)
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{
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struct mxc_scc *scc = ctx->scc;
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int nents;
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nents = sg_nents_for_len(req->src, req->nbytes);
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if (nents < 0) {
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dev_err(scc->dev, "Invalid number of src SC");
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return nents;
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}
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ctx->src_nents = nents;
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nents = sg_nents_for_len(req->dst, req->nbytes);
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if (nents < 0) {
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dev_err(scc->dev, "Invalid number of dst SC");
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return nents;
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}
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ctx->dst_nents = nents;
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ctx->size = 0;
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ctx->offset = 0;
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return 0;
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}
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static int mxc_scc_ablkcipher_req_complete(struct crypto_async_request *req,
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struct mxc_scc_ctx *ctx,
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int result)
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{
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struct ablkcipher_request *ablkreq = ablkcipher_request_cast(req);
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struct mxc_scc *scc = ctx->scc;
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scc->req = NULL;
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scc->bytes_remaining = scc->memory_size_bytes;
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if (ctx->ctrl & SCC_SCM_CTRL_CBC_MODE)
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memcpy(ablkreq->info, scc->base + SCC_SCM_INIT_VECTOR_0,
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scc->block_size_bytes);
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req->complete(req, result);
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scc->hw_busy = false;
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return 0;
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}
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static int mxc_scc_put_data(struct mxc_scc_ctx *ctx,
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struct ablkcipher_request *req)
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{
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u8 padding_buffer[sizeof(u16) + sizeof(scc_block_padding)];
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size_t len = min_t(size_t, req->nbytes - ctx->offset,
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ctx->scc->bytes_remaining);
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unsigned int padding_byte_count = 0;
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struct mxc_scc *scc = ctx->scc;
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void __iomem *to;
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if (ctx->ctrl & SCC_SCM_CTRL_DECRYPT_MODE)
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to = scc->black_memory;
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else
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to = scc->red_memory;
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if (ctx->ctrl & SCC_SCM_CTRL_CBC_MODE && req->info)
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memcpy(scc->base + SCC_SCM_INIT_VECTOR_0, req->info,
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scc->block_size_bytes);
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len = sg_pcopy_to_buffer(req->src, ctx->src_nents,
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to, len, ctx->offset);
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if (!len) {
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dev_err(scc->dev, "pcopy err to 0x%p (len=%d)\n", to, len);
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return -EINVAL;
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}
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ctx->size = len;
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#ifdef DEBUG
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dev_dbg(scc->dev, "copied %d bytes to 0x%p\n", len, to);
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print_hex_dump(KERN_ERR,
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"init vector0@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4,
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scc->base + SCC_SCM_INIT_VECTOR_0, scc->block_size_bytes,
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1);
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print_hex_dump(KERN_ERR,
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"red memory@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4,
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scc->red_memory, ctx->size, 1);
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print_hex_dump(KERN_ERR,
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"black memory@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4,
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scc->black_memory, ctx->size, 1);
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#endif
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scc->bytes_remaining -= len;
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padding_byte_count = len % scc->block_size_bytes;
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if (padding_byte_count) {
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memcpy(padding_buffer, scc_block_padding, padding_byte_count);
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memcpy(to + len, padding_buffer, padding_byte_count);
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ctx->size += padding_byte_count;
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR,
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"data to encrypt@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4,
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to, ctx->size, 1);
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#endif
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return 0;
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}
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static void mxc_scc_ablkcipher_next(struct mxc_scc_ctx *ctx,
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struct crypto_async_request *req)
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{
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struct ablkcipher_request *ablkreq = ablkcipher_request_cast(req);
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struct mxc_scc *scc = ctx->scc;
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int err;
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dev_dbg(scc->dev, "dispatch request (nbytes=%d, src=%p, dst=%p)\n",
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ablkreq->nbytes, ablkreq->src, ablkreq->dst);
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writel(0, scc->base + SCC_SCM_ERROR_STATUS);
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err = mxc_scc_put_data(ctx, ablkreq);
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if (err) {
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mxc_scc_ablkcipher_req_complete(req, ctx, err);
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return;
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}
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dev_dbg(scc->dev, "Start encryption (0x%p/0x%p)\n",
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(void *)readl(scc->base + SCC_SCM_RED_START),
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(void *)readl(scc->base + SCC_SCM_BLACK_START));
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/* clear interrupt control registers */
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writel(SCC_SCM_INTR_CTRL_CLR_INTR,
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scc->base + SCC_SCM_INTR_CTRL);
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writel((ctx->size / ctx->scc->block_size_bytes) - 1,
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scc->base + SCC_SCM_LENGTH);
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dev_dbg(scc->dev, "Process %d block(s) in 0x%p\n",
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ctx->size / ctx->scc->block_size_bytes,
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(ctx->ctrl & SCC_SCM_CTRL_DECRYPT_MODE) ? scc->black_memory :
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scc->red_memory);
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writel(ctx->ctrl, scc->base + SCC_SCM_CTRL);
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}
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static irqreturn_t mxc_scc_int(int irq, void *priv)
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{
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struct crypto_async_request *req;
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struct mxc_scc_ctx *ctx;
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struct mxc_scc *scc = priv;
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int status;
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int ret;
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status = readl(scc->base + SCC_SCM_STATUS);
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/* clear interrupt control registers */
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writel(SCC_SCM_INTR_CTRL_CLR_INTR, scc->base + SCC_SCM_INTR_CTRL);
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if (status & SCC_SCM_STATUS_BUSY)
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return IRQ_NONE;
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req = scc->req;
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if (req) {
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ctx = crypto_tfm_ctx(req->tfm);
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ret = mxc_scc_get_data(ctx, req);
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if (ret != -EINPROGRESS)
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mxc_scc_ablkcipher_req_complete(req, ctx, ret);
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else
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mxc_scc_ablkcipher_next(ctx, req);
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}
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return IRQ_HANDLED;
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}
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static int mxc_scc_cra_init(struct crypto_tfm *tfm)
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{
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struct mxc_scc_ctx *ctx = crypto_tfm_ctx(tfm);
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struct crypto_alg *alg = tfm->__crt_alg;
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struct mxc_scc_crypto_tmpl *algt;
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algt = container_of(alg, struct mxc_scc_crypto_tmpl, alg);
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ctx->scc = algt->scc;
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return 0;
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}
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static void mxc_scc_dequeue_req_unlocked(struct mxc_scc_ctx *ctx)
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{
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struct crypto_async_request *req, *backlog;
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if (ctx->scc->hw_busy)
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return;
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spin_lock_bh(&ctx->scc->lock);
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backlog = crypto_get_backlog(&ctx->scc->queue);
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req = crypto_dequeue_request(&ctx->scc->queue);
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ctx->scc->req = req;
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ctx->scc->hw_busy = true;
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spin_unlock_bh(&ctx->scc->lock);
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if (!req)
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return;
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if (backlog)
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backlog->complete(backlog, -EINPROGRESS);
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mxc_scc_ablkcipher_next(ctx, req);
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}
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static int mxc_scc_queue_req(struct mxc_scc_ctx *ctx,
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struct crypto_async_request *req)
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{
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int ret;
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spin_lock_bh(&ctx->scc->lock);
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ret = crypto_enqueue_request(&ctx->scc->queue, req);
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spin_unlock_bh(&ctx->scc->lock);
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if (ret != -EINPROGRESS)
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return ret;
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mxc_scc_dequeue_req_unlocked(ctx);
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return -EINPROGRESS;
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}
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static int mxc_scc_des3_op(struct mxc_scc_ctx *ctx,
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struct ablkcipher_request *req)
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{
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int err;
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err = mxc_scc_ablkcipher_req_init(req, ctx);
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if (err)
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return err;
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return mxc_scc_queue_req(ctx, &req->base);
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}
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static int mxc_scc_ecb_des_encrypt(struct ablkcipher_request *req)
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{
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struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
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struct mxc_scc_ctx *ctx = crypto_ablkcipher_ctx(cipher);
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ctx->ctrl = SCC_SCM_CTRL_START_CIPHER;
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return mxc_scc_des3_op(ctx, req);
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}
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static int mxc_scc_ecb_des_decrypt(struct ablkcipher_request *req)
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{
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struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
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struct mxc_scc_ctx *ctx = crypto_ablkcipher_ctx(cipher);
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ctx->ctrl = SCC_SCM_CTRL_START_CIPHER;
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ctx->ctrl |= SCC_SCM_CTRL_DECRYPT_MODE;
|
|
|
|
return mxc_scc_des3_op(ctx, req);
|
|
}
|
|
|
|
static int mxc_scc_cbc_des_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
|
|
struct mxc_scc_ctx *ctx = crypto_ablkcipher_ctx(cipher);
|
|
|
|
ctx->ctrl = SCC_SCM_CTRL_START_CIPHER;
|
|
ctx->ctrl |= SCC_SCM_CTRL_CBC_MODE;
|
|
|
|
return mxc_scc_des3_op(ctx, req);
|
|
}
|
|
|
|
static int mxc_scc_cbc_des_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
|
|
struct mxc_scc_ctx *ctx = crypto_ablkcipher_ctx(cipher);
|
|
|
|
ctx->ctrl = SCC_SCM_CTRL_START_CIPHER;
|
|
ctx->ctrl |= SCC_SCM_CTRL_CBC_MODE;
|
|
ctx->ctrl |= SCC_SCM_CTRL_DECRYPT_MODE;
|
|
|
|
return mxc_scc_des3_op(ctx, req);
|
|
}
|
|
|
|
static void mxc_scc_hw_init(struct mxc_scc *scc)
|
|
{
|
|
int offset;
|
|
|
|
offset = SCC_NON_RESERVED_OFFSET / scc->block_size_bytes;
|
|
|
|
/* Fill the RED_START register */
|
|
writel(offset, scc->base + SCC_SCM_RED_START);
|
|
|
|
/* Fill the BLACK_START register */
|
|
writel(offset, scc->base + SCC_SCM_BLACK_START);
|
|
|
|
scc->red_memory = scc->base + SCC_SCM_RED_MEMORY +
|
|
SCC_NON_RESERVED_OFFSET;
|
|
|
|
scc->black_memory = scc->base + SCC_SCM_BLACK_MEMORY +
|
|
SCC_NON_RESERVED_OFFSET;
|
|
|
|
scc->bytes_remaining = scc->memory_size_bytes;
|
|
}
|
|
|
|
static int mxc_scc_get_config(struct mxc_scc *scc)
|
|
{
|
|
int config;
|
|
|
|
config = readl(scc->base + SCC_SCM_CFG);
|
|
|
|
scc->block_size_bytes = config & SCC_SCM_CFG_BLOCK_SIZE_MASK;
|
|
|
|
scc->black_ram_size_blocks = config & SCC_SCM_CFG_BLACK_SIZE_MASK;
|
|
|
|
scc->memory_size_bytes = (scc->block_size_bytes *
|
|
scc->black_ram_size_blocks) -
|
|
SCC_NON_RESERVED_OFFSET;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static enum mxc_scc_state mxc_scc_get_state(struct mxc_scc *scc)
|
|
{
|
|
enum mxc_scc_state state;
|
|
int status;
|
|
|
|
status = readl(scc->base + SCC_SMN_STATUS) &
|
|
SCC_SMN_STATUS_STATE_MASK;
|
|
|
|
/* If in Health Check, try to bringup to secure state */
|
|
if (status & SCC_SMN_STATE_HEALTH_CHECK) {
|
|
/*
|
|
* Write a simple algorithm to the Algorithm Sequence
|
|
* Checker (ASC)
|
|
*/
|
|
writel(0xaaaa, scc->base + SCC_SMN_SEQ_START);
|
|
writel(0x5555, scc->base + SCC_SMN_SEQ_END);
|
|
writel(0x5555, scc->base + SCC_SMN_SEQ_CHECK);
|
|
|
|
status = readl(scc->base + SCC_SMN_STATUS) &
|
|
SCC_SMN_STATUS_STATE_MASK;
|
|
}
|
|
|
|
switch (status) {
|
|
case SCC_SMN_STATE_NON_SECURE:
|
|
case SCC_SMN_STATE_SECURE:
|
|
state = SCC_STATE_OK;
|
|
break;
|
|
case SCC_SMN_STATE_FAIL:
|
|
state = SCC_STATE_FAILED;
|
|
break;
|
|
default:
|
|
state = SCC_STATE_UNIMPLEMENTED;
|
|
break;
|
|
}
|
|
|
|
return state;
|
|
}
|
|
|
|
static struct mxc_scc_crypto_tmpl scc_ecb_des = {
|
|
.alg = {
|
|
.cra_name = "ecb(des3_ede)",
|
|
.cra_driver_name = "ecb-des3-scc",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct mxc_scc_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = mxc_scc_cra_init,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
.encrypt = mxc_scc_ecb_des_encrypt,
|
|
.decrypt = mxc_scc_ecb_des_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
static struct mxc_scc_crypto_tmpl scc_cbc_des = {
|
|
.alg = {
|
|
.cra_name = "cbc(des3_ede)",
|
|
.cra_driver_name = "cbc-des3-scc",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct mxc_scc_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = mxc_scc_cra_init,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
.encrypt = mxc_scc_cbc_des_encrypt,
|
|
.decrypt = mxc_scc_cbc_des_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
static struct mxc_scc_crypto_tmpl *scc_crypto_algs[] = {
|
|
&scc_ecb_des,
|
|
&scc_cbc_des,
|
|
};
|
|
|
|
static int mxc_scc_crypto_register(struct mxc_scc *scc)
|
|
{
|
|
int i;
|
|
int err = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(scc_crypto_algs); i++) {
|
|
scc_crypto_algs[i]->scc = scc;
|
|
err = crypto_register_alg(&scc_crypto_algs[i]->alg);
|
|
if (err)
|
|
goto err_out;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
while (--i >= 0)
|
|
crypto_unregister_alg(&scc_crypto_algs[i]->alg);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void mxc_scc_crypto_unregister(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(scc_crypto_algs); i++)
|
|
crypto_unregister_alg(&scc_crypto_algs[i]->alg);
|
|
}
|
|
|
|
static int mxc_scc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res;
|
|
struct mxc_scc *scc;
|
|
enum mxc_scc_state state;
|
|
int irq;
|
|
int ret;
|
|
int i;
|
|
|
|
scc = devm_kzalloc(dev, sizeof(*scc), GFP_KERNEL);
|
|
if (!scc)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
scc->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(scc->base))
|
|
return PTR_ERR(scc->base);
|
|
|
|
scc->clk = devm_clk_get(&pdev->dev, "ipg");
|
|
if (IS_ERR(scc->clk)) {
|
|
dev_err(dev, "Could not get ipg clock\n");
|
|
return PTR_ERR(scc->clk);
|
|
}
|
|
|
|
ret = clk_prepare_enable(scc->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* clear error status register */
|
|
writel(0x0, scc->base + SCC_SCM_ERROR_STATUS);
|
|
|
|
/* clear interrupt control registers */
|
|
writel(SCC_SCM_INTR_CTRL_CLR_INTR |
|
|
SCC_SCM_INTR_CTRL_MASK_INTR,
|
|
scc->base + SCC_SCM_INTR_CTRL);
|
|
|
|
writel(SCC_SMN_COMMAND_CLR_INTR |
|
|
SCC_SMN_COMMAND_EN_INTR,
|
|
scc->base + SCC_SMN_COMMAND);
|
|
|
|
scc->dev = dev;
|
|
platform_set_drvdata(pdev, scc);
|
|
|
|
ret = mxc_scc_get_config(scc);
|
|
if (ret)
|
|
goto err_out;
|
|
|
|
state = mxc_scc_get_state(scc);
|
|
|
|
if (state != SCC_STATE_OK) {
|
|
dev_err(dev, "SCC in unusable state %d\n", state);
|
|
ret = -EINVAL;
|
|
goto err_out;
|
|
}
|
|
|
|
mxc_scc_hw_init(scc);
|
|
|
|
spin_lock_init(&scc->lock);
|
|
/* FIXME: calculate queue from RAM slots */
|
|
crypto_init_queue(&scc->queue, 50);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
irq = platform_get_irq(pdev, i);
|
|
if (irq < 0) {
|
|
dev_err(dev, "failed to get irq resource: %d\n", irq);
|
|
ret = irq;
|
|
goto err_out;
|
|
}
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, NULL, mxc_scc_int,
|
|
IRQF_ONESHOT, dev_name(dev), scc);
|
|
if (ret)
|
|
goto err_out;
|
|
}
|
|
|
|
ret = mxc_scc_crypto_register(scc);
|
|
if (ret) {
|
|
dev_err(dev, "could not register algorithms");
|
|
goto err_out;
|
|
}
|
|
|
|
dev_info(dev, "registered successfully.\n");
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
clk_disable_unprepare(scc->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mxc_scc_remove(struct platform_device *pdev)
|
|
{
|
|
struct mxc_scc *scc = platform_get_drvdata(pdev);
|
|
|
|
mxc_scc_crypto_unregister();
|
|
|
|
clk_disable_unprepare(scc->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mxc_scc_dt_ids[] = {
|
|
{ .compatible = "fsl,imx25-scc", .data = NULL, },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mxc_scc_dt_ids);
|
|
|
|
static struct platform_driver mxc_scc_driver = {
|
|
.probe = mxc_scc_probe,
|
|
.remove = mxc_scc_remove,
|
|
.driver = {
|
|
.name = "mxc-scc",
|
|
.of_match_table = mxc_scc_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mxc_scc_driver);
|
|
MODULE_AUTHOR("Steffen Trumtrar <kernel@pengutronix.de>");
|
|
MODULE_DESCRIPTION("Freescale i.MX25 SCC Crypto driver");
|
|
MODULE_LICENSE("GPL v2");
|