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![Tero Kristo](/assets/img/avatar_default.png)
Crypto driver queue size can now be configured from userspace. This allows optimizing the queue usage based on use case. Default queue size is still 10 entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
1351 lines
32 KiB
C
1351 lines
32 KiB
C
/*
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* Cryptographic API.
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*
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* Support for OMAP AES HW acceleration.
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*
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* Copyright (c) 2010 Nokia Corporation
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* Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
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* Copyright (c) 2011 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#define pr_fmt(fmt) "%20s: " fmt, __func__
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#define prn(num) pr_debug(#num "=%d\n", num)
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#define prx(num) pr_debug(#num "=%x\n", num)
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/crypto.h>
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#include <linux/interrupt.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/aes.h>
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#include <crypto/gcm.h>
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#include <crypto/engine.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/internal/aead.h>
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#include "omap-crypto.h"
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#include "omap-aes.h"
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/* keep registered devices data here */
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static LIST_HEAD(dev_list);
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static DEFINE_SPINLOCK(list_lock);
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static int aes_fallback_sz = 200;
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#ifdef DEBUG
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#define omap_aes_read(dd, offset) \
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({ \
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int _read_ret; \
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_read_ret = __raw_readl(dd->io_base + offset); \
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pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
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offset, _read_ret); \
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_read_ret; \
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})
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#else
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inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
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{
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return __raw_readl(dd->io_base + offset);
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}
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#endif
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#ifdef DEBUG
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#define omap_aes_write(dd, offset, value) \
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do { \
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pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
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offset, value); \
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__raw_writel(value, dd->io_base + offset); \
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} while (0)
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#else
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inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
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u32 value)
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{
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__raw_writel(value, dd->io_base + offset);
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}
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#endif
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static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
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u32 value, u32 mask)
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{
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u32 val;
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val = omap_aes_read(dd, offset);
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val &= ~mask;
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val |= value;
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omap_aes_write(dd, offset, val);
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}
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static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
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u32 *value, int count)
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{
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for (; count--; value++, offset += 4)
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omap_aes_write(dd, offset, *value);
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}
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static int omap_aes_hw_init(struct omap_aes_dev *dd)
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{
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int err;
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if (!(dd->flags & FLAGS_INIT)) {
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dd->flags |= FLAGS_INIT;
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dd->err = 0;
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}
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err = pm_runtime_get_sync(dd->dev);
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if (err < 0) {
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dev_err(dd->dev, "failed to get sync: %d\n", err);
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return err;
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}
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return 0;
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}
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void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
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{
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dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
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dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
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dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
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}
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int omap_aes_write_ctrl(struct omap_aes_dev *dd)
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{
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struct omap_aes_reqctx *rctx;
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unsigned int key32;
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int i, err;
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u32 val;
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err = omap_aes_hw_init(dd);
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if (err)
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return err;
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key32 = dd->ctx->keylen / sizeof(u32);
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/* RESET the key as previous HASH keys should not get affected*/
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if (dd->flags & FLAGS_GCM)
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for (i = 0; i < 0x40; i = i + 4)
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omap_aes_write(dd, i, 0x0);
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for (i = 0; i < key32; i++) {
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omap_aes_write(dd, AES_REG_KEY(dd, i),
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__le32_to_cpu(dd->ctx->key[i]));
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}
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if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
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omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
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if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
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rctx = aead_request_ctx(dd->aead_req);
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omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
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}
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val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
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if (dd->flags & FLAGS_CBC)
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val |= AES_REG_CTRL_CBC;
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if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
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val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
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if (dd->flags & FLAGS_GCM)
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val |= AES_REG_CTRL_GCM;
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if (dd->flags & FLAGS_ENCRYPT)
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val |= AES_REG_CTRL_DIRECTION;
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omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
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return 0;
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}
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static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
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{
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u32 mask, val;
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val = dd->pdata->dma_start;
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if (dd->dma_lch_out != NULL)
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val |= dd->pdata->dma_enable_out;
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if (dd->dma_lch_in != NULL)
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val |= dd->pdata->dma_enable_in;
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mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
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dd->pdata->dma_start;
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omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
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}
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static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
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{
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omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
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omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
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if (dd->flags & FLAGS_GCM)
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omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
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omap_aes_dma_trigger_omap2(dd, length);
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}
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static void omap_aes_dma_stop(struct omap_aes_dev *dd)
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{
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u32 mask;
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mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
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dd->pdata->dma_start;
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omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
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}
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struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
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{
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struct omap_aes_dev *dd;
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spin_lock_bh(&list_lock);
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dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
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list_move_tail(&dd->list, &dev_list);
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rctx->dd = dd;
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spin_unlock_bh(&list_lock);
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return dd;
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}
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static void omap_aes_dma_out_callback(void *data)
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{
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struct omap_aes_dev *dd = data;
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/* dma_lch_out - completed */
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tasklet_schedule(&dd->done_task);
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}
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static int omap_aes_dma_init(struct omap_aes_dev *dd)
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{
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int err;
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dd->dma_lch_out = NULL;
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dd->dma_lch_in = NULL;
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dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
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if (IS_ERR(dd->dma_lch_in)) {
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dev_err(dd->dev, "Unable to request in DMA channel\n");
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return PTR_ERR(dd->dma_lch_in);
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}
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dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
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if (IS_ERR(dd->dma_lch_out)) {
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dev_err(dd->dev, "Unable to request out DMA channel\n");
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err = PTR_ERR(dd->dma_lch_out);
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goto err_dma_out;
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}
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return 0;
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err_dma_out:
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dma_release_channel(dd->dma_lch_in);
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return err;
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}
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static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
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{
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if (dd->pio_only)
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return;
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dma_release_channel(dd->dma_lch_out);
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dma_release_channel(dd->dma_lch_in);
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}
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static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
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struct scatterlist *in_sg,
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struct scatterlist *out_sg,
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int in_sg_len, int out_sg_len)
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{
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struct dma_async_tx_descriptor *tx_in, *tx_out;
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struct dma_slave_config cfg;
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int ret;
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if (dd->pio_only) {
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scatterwalk_start(&dd->in_walk, dd->in_sg);
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scatterwalk_start(&dd->out_walk, dd->out_sg);
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/* Enable DATAIN interrupt and let it take
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care of the rest */
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omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
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return 0;
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}
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dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
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memset(&cfg, 0, sizeof(cfg));
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cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
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cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.src_maxburst = DST_MAXBURST;
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cfg.dst_maxburst = DST_MAXBURST;
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/* IN */
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ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
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if (ret) {
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dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
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ret);
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return ret;
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}
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tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!tx_in) {
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dev_err(dd->dev, "IN prep_slave_sg() failed\n");
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return -EINVAL;
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}
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/* No callback necessary */
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tx_in->callback_param = dd;
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/* OUT */
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ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
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if (ret) {
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dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
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ret);
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return ret;
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}
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tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!tx_out) {
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dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
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return -EINVAL;
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}
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if (dd->flags & FLAGS_GCM)
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tx_out->callback = omap_aes_gcm_dma_out_callback;
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else
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tx_out->callback = omap_aes_dma_out_callback;
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tx_out->callback_param = dd;
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dmaengine_submit(tx_in);
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dmaengine_submit(tx_out);
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dma_async_issue_pending(dd->dma_lch_in);
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dma_async_issue_pending(dd->dma_lch_out);
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/* start DMA */
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dd->pdata->trigger(dd, dd->total);
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return 0;
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}
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int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
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{
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int err;
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pr_debug("total: %d\n", dd->total);
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if (!dd->pio_only) {
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err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
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DMA_TO_DEVICE);
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if (!err) {
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dev_err(dd->dev, "dma_map_sg() error\n");
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return -EINVAL;
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}
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err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
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DMA_FROM_DEVICE);
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if (!err) {
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dev_err(dd->dev, "dma_map_sg() error\n");
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return -EINVAL;
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}
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}
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err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
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dd->out_sg_len);
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if (err && !dd->pio_only) {
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dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
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dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
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DMA_FROM_DEVICE);
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}
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return err;
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}
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static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
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{
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struct ablkcipher_request *req = dd->req;
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pr_debug("err: %d\n", err);
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crypto_finalize_ablkcipher_request(dd->engine, req, err);
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pm_runtime_mark_last_busy(dd->dev);
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pm_runtime_put_autosuspend(dd->dev);
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}
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int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
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{
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pr_debug("total: %d\n", dd->total);
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omap_aes_dma_stop(dd);
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return 0;
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}
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static int omap_aes_handle_queue(struct omap_aes_dev *dd,
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struct ablkcipher_request *req)
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{
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if (req)
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return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
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return 0;
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}
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static int omap_aes_prepare_req(struct crypto_engine *engine,
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void *areq)
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{
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struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
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struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
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crypto_ablkcipher_reqtfm(req));
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struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
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struct omap_aes_dev *dd = rctx->dd;
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int ret;
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u16 flags;
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if (!dd)
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return -ENODEV;
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/* assign new request to device */
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dd->req = req;
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dd->total = req->nbytes;
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dd->total_save = req->nbytes;
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dd->in_sg = req->src;
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dd->out_sg = req->dst;
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dd->orig_out = req->dst;
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flags = OMAP_CRYPTO_COPY_DATA;
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if (req->src == req->dst)
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flags |= OMAP_CRYPTO_FORCE_COPY;
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ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
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dd->in_sgl, flags,
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FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
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if (ret)
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return ret;
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ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
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&dd->out_sgl, 0,
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FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
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if (ret)
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return ret;
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dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
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if (dd->in_sg_len < 0)
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return dd->in_sg_len;
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dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
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if (dd->out_sg_len < 0)
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return dd->out_sg_len;
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rctx->mode &= FLAGS_MODE_MASK;
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dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
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dd->ctx = ctx;
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rctx->dd = dd;
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return omap_aes_write_ctrl(dd);
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}
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static int omap_aes_crypt_req(struct crypto_engine *engine,
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void *areq)
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{
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struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
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struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
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struct omap_aes_dev *dd = rctx->dd;
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if (!dd)
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return -ENODEV;
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return omap_aes_crypt_dma_start(dd);
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}
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static void omap_aes_done_task(unsigned long data)
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{
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struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
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pr_debug("enter done_task\n");
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|
|
|
if (!dd->pio_only) {
|
|
dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
|
|
DMA_FROM_DEVICE);
|
|
dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
|
|
dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
|
|
DMA_FROM_DEVICE);
|
|
omap_aes_crypt_dma_stop(dd);
|
|
}
|
|
|
|
omap_crypto_cleanup(dd->in_sgl, NULL, 0, dd->total_save,
|
|
FLAGS_IN_DATA_ST_SHIFT, dd->flags);
|
|
|
|
omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
|
|
FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
|
|
|
|
omap_aes_finish_req(dd, 0);
|
|
|
|
pr_debug("exit\n");
|
|
}
|
|
|
|
static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
|
|
{
|
|
struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
|
|
crypto_ablkcipher_reqtfm(req));
|
|
struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
|
|
struct omap_aes_dev *dd;
|
|
int ret;
|
|
|
|
pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
|
|
!!(mode & FLAGS_ENCRYPT),
|
|
!!(mode & FLAGS_CBC));
|
|
|
|
if (req->nbytes < aes_fallback_sz) {
|
|
SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
|
|
|
|
skcipher_request_set_tfm(subreq, ctx->fallback);
|
|
skcipher_request_set_callback(subreq, req->base.flags, NULL,
|
|
NULL);
|
|
skcipher_request_set_crypt(subreq, req->src, req->dst,
|
|
req->nbytes, req->info);
|
|
|
|
if (mode & FLAGS_ENCRYPT)
|
|
ret = crypto_skcipher_encrypt(subreq);
|
|
else
|
|
ret = crypto_skcipher_decrypt(subreq);
|
|
|
|
skcipher_request_zero(subreq);
|
|
return ret;
|
|
}
|
|
dd = omap_aes_find_dev(rctx);
|
|
if (!dd)
|
|
return -ENODEV;
|
|
|
|
rctx->mode = mode;
|
|
|
|
return omap_aes_handle_queue(dd, req);
|
|
}
|
|
|
|
/* ********************** ALG API ************************************ */
|
|
|
|
static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
|
|
unsigned int keylen)
|
|
{
|
|
struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
|
|
int ret;
|
|
|
|
if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
|
|
keylen != AES_KEYSIZE_256)
|
|
return -EINVAL;
|
|
|
|
pr_debug("enter, keylen: %d\n", keylen);
|
|
|
|
memcpy(ctx->key, key, keylen);
|
|
ctx->keylen = keylen;
|
|
|
|
crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
|
|
crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
|
|
CRYPTO_TFM_REQ_MASK);
|
|
|
|
ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
|
|
if (!ret)
|
|
return 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, 0);
|
|
}
|
|
|
|
static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
|
|
}
|
|
|
|
static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_CBC);
|
|
}
|
|
|
|
static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
|
|
}
|
|
|
|
static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return omap_aes_crypt(req, FLAGS_CTR);
|
|
}
|
|
|
|
static int omap_aes_prepare_req(struct crypto_engine *engine,
|
|
void *req);
|
|
static int omap_aes_crypt_req(struct crypto_engine *engine,
|
|
void *req);
|
|
|
|
static int omap_aes_cra_init(struct crypto_tfm *tfm)
|
|
{
|
|
const char *name = crypto_tfm_alg_name(tfm);
|
|
const u32 flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
|
|
struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct crypto_skcipher *blk;
|
|
|
|
blk = crypto_alloc_skcipher(name, 0, flags);
|
|
if (IS_ERR(blk))
|
|
return PTR_ERR(blk);
|
|
|
|
ctx->fallback = blk;
|
|
|
|
tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
|
|
|
|
ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
|
|
ctx->enginectx.op.unprepare_request = NULL;
|
|
ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_aes_gcm_cra_init(struct crypto_aead *tfm)
|
|
{
|
|
struct omap_aes_dev *dd = NULL;
|
|
struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
|
|
int err;
|
|
|
|
/* Find AES device, currently picks the first device */
|
|
spin_lock_bh(&list_lock);
|
|
list_for_each_entry(dd, &dev_list, list) {
|
|
break;
|
|
}
|
|
spin_unlock_bh(&list_lock);
|
|
|
|
err = pm_runtime_get_sync(dd->dev);
|
|
if (err < 0) {
|
|
dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
|
|
__func__, err);
|
|
return err;
|
|
}
|
|
|
|
tfm->reqsize = sizeof(struct omap_aes_reqctx);
|
|
ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0);
|
|
if (IS_ERR(ctx->ctr)) {
|
|
pr_warn("could not load aes driver for encrypting IV\n");
|
|
return PTR_ERR(ctx->ctr);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_aes_cra_exit(struct crypto_tfm *tfm)
|
|
{
|
|
struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
if (ctx->fallback)
|
|
crypto_free_skcipher(ctx->fallback);
|
|
|
|
ctx->fallback = NULL;
|
|
}
|
|
|
|
static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm)
|
|
{
|
|
struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
|
|
|
|
omap_aes_cra_exit(crypto_aead_tfm(tfm));
|
|
|
|
if (ctx->ctr)
|
|
crypto_free_skcipher(ctx->ctr);
|
|
}
|
|
|
|
/* ********************** ALGS ************************************ */
|
|
|
|
static struct crypto_alg algs_ecb_cbc[] = {
|
|
{
|
|
.cra_name = "ecb(aes)",
|
|
.cra_driver_name = "ecb-aes-omap",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_aes_cra_init,
|
|
.cra_exit = omap_aes_cra_exit,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.setkey = omap_aes_setkey,
|
|
.encrypt = omap_aes_ecb_encrypt,
|
|
.decrypt = omap_aes_ecb_decrypt,
|
|
}
|
|
},
|
|
{
|
|
.cra_name = "cbc(aes)",
|
|
.cra_driver_name = "cbc-aes-omap",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_aes_cra_init,
|
|
.cra_exit = omap_aes_cra_exit,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.setkey = omap_aes_setkey,
|
|
.encrypt = omap_aes_cbc_encrypt,
|
|
.decrypt = omap_aes_cbc_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
static struct crypto_alg algs_ctr[] = {
|
|
{
|
|
.cra_name = "ctr(aes)",
|
|
.cra_driver_name = "ctr-aes-omap",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_aes_cra_init,
|
|
.cra_exit = omap_aes_cra_exit,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.geniv = "eseqiv",
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.setkey = omap_aes_setkey,
|
|
.encrypt = omap_aes_ctr_encrypt,
|
|
.decrypt = omap_aes_ctr_decrypt,
|
|
}
|
|
} ,
|
|
};
|
|
|
|
static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
|
|
{
|
|
.algs_list = algs_ecb_cbc,
|
|
.size = ARRAY_SIZE(algs_ecb_cbc),
|
|
},
|
|
};
|
|
|
|
static struct aead_alg algs_aead_gcm[] = {
|
|
{
|
|
.base = {
|
|
.cra_name = "gcm(aes)",
|
|
.cra_driver_name = "gcm-aes-omap",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = 1,
|
|
.cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
.cra_alignmask = 0xf,
|
|
.cra_module = THIS_MODULE,
|
|
},
|
|
.init = omap_aes_gcm_cra_init,
|
|
.exit = omap_aes_gcm_cra_exit,
|
|
.ivsize = GCM_AES_IV_SIZE,
|
|
.maxauthsize = AES_BLOCK_SIZE,
|
|
.setkey = omap_aes_gcm_setkey,
|
|
.encrypt = omap_aes_gcm_encrypt,
|
|
.decrypt = omap_aes_gcm_decrypt,
|
|
},
|
|
{
|
|
.base = {
|
|
.cra_name = "rfc4106(gcm(aes))",
|
|
.cra_driver_name = "rfc4106-gcm-aes-omap",
|
|
.cra_priority = 300,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = 1,
|
|
.cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
.cra_alignmask = 0xf,
|
|
.cra_module = THIS_MODULE,
|
|
},
|
|
.init = omap_aes_gcm_cra_init,
|
|
.exit = omap_aes_gcm_cra_exit,
|
|
.maxauthsize = AES_BLOCK_SIZE,
|
|
.ivsize = GCM_RFC4106_IV_SIZE,
|
|
.setkey = omap_aes_4106gcm_setkey,
|
|
.encrypt = omap_aes_4106gcm_encrypt,
|
|
.decrypt = omap_aes_4106gcm_decrypt,
|
|
},
|
|
};
|
|
|
|
static struct omap_aes_aead_algs omap_aes_aead_info = {
|
|
.algs_list = algs_aead_gcm,
|
|
.size = ARRAY_SIZE(algs_aead_gcm),
|
|
};
|
|
|
|
static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
|
|
.algs_info = omap_aes_algs_info_ecb_cbc,
|
|
.algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
|
|
.trigger = omap_aes_dma_trigger_omap2,
|
|
.key_ofs = 0x1c,
|
|
.iv_ofs = 0x20,
|
|
.ctrl_ofs = 0x30,
|
|
.data_ofs = 0x34,
|
|
.rev_ofs = 0x44,
|
|
.mask_ofs = 0x48,
|
|
.dma_enable_in = BIT(2),
|
|
.dma_enable_out = BIT(3),
|
|
.dma_start = BIT(5),
|
|
.major_mask = 0xf0,
|
|
.major_shift = 4,
|
|
.minor_mask = 0x0f,
|
|
.minor_shift = 0,
|
|
};
|
|
|
|
#ifdef CONFIG_OF
|
|
static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
|
|
{
|
|
.algs_list = algs_ecb_cbc,
|
|
.size = ARRAY_SIZE(algs_ecb_cbc),
|
|
},
|
|
{
|
|
.algs_list = algs_ctr,
|
|
.size = ARRAY_SIZE(algs_ctr),
|
|
},
|
|
};
|
|
|
|
static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
|
|
.algs_info = omap_aes_algs_info_ecb_cbc_ctr,
|
|
.algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
|
|
.trigger = omap_aes_dma_trigger_omap2,
|
|
.key_ofs = 0x1c,
|
|
.iv_ofs = 0x20,
|
|
.ctrl_ofs = 0x30,
|
|
.data_ofs = 0x34,
|
|
.rev_ofs = 0x44,
|
|
.mask_ofs = 0x48,
|
|
.dma_enable_in = BIT(2),
|
|
.dma_enable_out = BIT(3),
|
|
.dma_start = BIT(5),
|
|
.major_mask = 0xf0,
|
|
.major_shift = 4,
|
|
.minor_mask = 0x0f,
|
|
.minor_shift = 0,
|
|
};
|
|
|
|
static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
|
|
.algs_info = omap_aes_algs_info_ecb_cbc_ctr,
|
|
.algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
|
|
.aead_algs_info = &omap_aes_aead_info,
|
|
.trigger = omap_aes_dma_trigger_omap4,
|
|
.key_ofs = 0x3c,
|
|
.iv_ofs = 0x40,
|
|
.ctrl_ofs = 0x50,
|
|
.data_ofs = 0x60,
|
|
.rev_ofs = 0x80,
|
|
.mask_ofs = 0x84,
|
|
.irq_status_ofs = 0x8c,
|
|
.irq_enable_ofs = 0x90,
|
|
.dma_enable_in = BIT(5),
|
|
.dma_enable_out = BIT(6),
|
|
.major_mask = 0x0700,
|
|
.major_shift = 8,
|
|
.minor_mask = 0x003f,
|
|
.minor_shift = 0,
|
|
};
|
|
|
|
static irqreturn_t omap_aes_irq(int irq, void *dev_id)
|
|
{
|
|
struct omap_aes_dev *dd = dev_id;
|
|
u32 status, i;
|
|
u32 *src, *dst;
|
|
|
|
status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
|
|
if (status & AES_REG_IRQ_DATA_IN) {
|
|
omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
|
|
|
|
BUG_ON(!dd->in_sg);
|
|
|
|
BUG_ON(_calc_walked(in) > dd->in_sg->length);
|
|
|
|
src = sg_virt(dd->in_sg) + _calc_walked(in);
|
|
|
|
for (i = 0; i < AES_BLOCK_WORDS; i++) {
|
|
omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
|
|
|
|
scatterwalk_advance(&dd->in_walk, 4);
|
|
if (dd->in_sg->length == _calc_walked(in)) {
|
|
dd->in_sg = sg_next(dd->in_sg);
|
|
if (dd->in_sg) {
|
|
scatterwalk_start(&dd->in_walk,
|
|
dd->in_sg);
|
|
src = sg_virt(dd->in_sg) +
|
|
_calc_walked(in);
|
|
}
|
|
} else {
|
|
src++;
|
|
}
|
|
}
|
|
|
|
/* Clear IRQ status */
|
|
status &= ~AES_REG_IRQ_DATA_IN;
|
|
omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
|
|
|
|
/* Enable DATA_OUT interrupt */
|
|
omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
|
|
|
|
} else if (status & AES_REG_IRQ_DATA_OUT) {
|
|
omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
|
|
|
|
BUG_ON(!dd->out_sg);
|
|
|
|
BUG_ON(_calc_walked(out) > dd->out_sg->length);
|
|
|
|
dst = sg_virt(dd->out_sg) + _calc_walked(out);
|
|
|
|
for (i = 0; i < AES_BLOCK_WORDS; i++) {
|
|
*dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
|
|
scatterwalk_advance(&dd->out_walk, 4);
|
|
if (dd->out_sg->length == _calc_walked(out)) {
|
|
dd->out_sg = sg_next(dd->out_sg);
|
|
if (dd->out_sg) {
|
|
scatterwalk_start(&dd->out_walk,
|
|
dd->out_sg);
|
|
dst = sg_virt(dd->out_sg) +
|
|
_calc_walked(out);
|
|
}
|
|
} else {
|
|
dst++;
|
|
}
|
|
}
|
|
|
|
dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
|
|
|
|
/* Clear IRQ status */
|
|
status &= ~AES_REG_IRQ_DATA_OUT;
|
|
omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
|
|
|
|
if (!dd->total)
|
|
/* All bytes read! */
|
|
tasklet_schedule(&dd->done_task);
|
|
else
|
|
/* Enable DATA_IN interrupt for next block */
|
|
omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct of_device_id omap_aes_of_match[] = {
|
|
{
|
|
.compatible = "ti,omap2-aes",
|
|
.data = &omap_aes_pdata_omap2,
|
|
},
|
|
{
|
|
.compatible = "ti,omap3-aes",
|
|
.data = &omap_aes_pdata_omap3,
|
|
},
|
|
{
|
|
.compatible = "ti,omap4-aes",
|
|
.data = &omap_aes_pdata_omap4,
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, omap_aes_of_match);
|
|
|
|
static int omap_aes_get_res_of(struct omap_aes_dev *dd,
|
|
struct device *dev, struct resource *res)
|
|
{
|
|
struct device_node *node = dev->of_node;
|
|
int err = 0;
|
|
|
|
dd->pdata = of_device_get_match_data(dev);
|
|
if (!dd->pdata) {
|
|
dev_err(dev, "no compatible OF match\n");
|
|
err = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
err = of_address_to_resource(node, 0, res);
|
|
if (err < 0) {
|
|
dev_err(dev, "can't translate OF node address\n");
|
|
err = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
err:
|
|
return err;
|
|
}
|
|
#else
|
|
static const struct of_device_id omap_aes_of_match[] = {
|
|
{},
|
|
};
|
|
|
|
static int omap_aes_get_res_of(struct omap_aes_dev *dd,
|
|
struct device *dev, struct resource *res)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
|
|
struct platform_device *pdev, struct resource *res)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *r;
|
|
int err = 0;
|
|
|
|
/* Get the base address */
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!r) {
|
|
dev_err(dev, "no MEM resource info\n");
|
|
err = -ENODEV;
|
|
goto err;
|
|
}
|
|
memcpy(res, r, sizeof(*res));
|
|
|
|
/* Only OMAP2/3 can be non-DT */
|
|
dd->pdata = &omap_aes_pdata_omap2;
|
|
|
|
err:
|
|
return err;
|
|
}
|
|
|
|
static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
return sprintf(buf, "%d\n", aes_fallback_sz);
|
|
}
|
|
|
|
static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
|
|
const char *buf, size_t size)
|
|
{
|
|
ssize_t status;
|
|
long value;
|
|
|
|
status = kstrtol(buf, 0, &value);
|
|
if (status)
|
|
return status;
|
|
|
|
/* HW accelerator only works with buffers > 9 */
|
|
if (value < 9) {
|
|
dev_err(dev, "minimum fallback size 9\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
aes_fallback_sz = value;
|
|
|
|
return size;
|
|
}
|
|
|
|
static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct omap_aes_dev *dd = dev_get_drvdata(dev);
|
|
|
|
return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
|
|
}
|
|
|
|
static ssize_t queue_len_store(struct device *dev,
|
|
struct device_attribute *attr, const char *buf,
|
|
size_t size)
|
|
{
|
|
struct omap_aes_dev *dd;
|
|
ssize_t status;
|
|
long value;
|
|
unsigned long flags;
|
|
|
|
status = kstrtol(buf, 0, &value);
|
|
if (status)
|
|
return status;
|
|
|
|
if (value < 1)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Changing the queue size in fly is safe, if size becomes smaller
|
|
* than current size, it will just not accept new entries until
|
|
* it has shrank enough.
|
|
*/
|
|
spin_lock_bh(&list_lock);
|
|
list_for_each_entry(dd, &dev_list, list) {
|
|
spin_lock_irqsave(&dd->lock, flags);
|
|
dd->engine->queue.max_qlen = value;
|
|
dd->aead_queue.base.max_qlen = value;
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
}
|
|
spin_unlock_bh(&list_lock);
|
|
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(queue_len);
|
|
static DEVICE_ATTR_RW(fallback);
|
|
|
|
static struct attribute *omap_aes_attrs[] = {
|
|
&dev_attr_queue_len.attr,
|
|
&dev_attr_fallback.attr,
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group omap_aes_attr_group = {
|
|
.attrs = omap_aes_attrs,
|
|
};
|
|
|
|
static int omap_aes_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct omap_aes_dev *dd;
|
|
struct crypto_alg *algp;
|
|
struct aead_alg *aalg;
|
|
struct resource res;
|
|
int err = -ENOMEM, i, j, irq = -1;
|
|
u32 reg;
|
|
|
|
dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
|
|
if (dd == NULL) {
|
|
dev_err(dev, "unable to alloc data struct.\n");
|
|
goto err_data;
|
|
}
|
|
dd->dev = dev;
|
|
platform_set_drvdata(pdev, dd);
|
|
|
|
aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
|
|
|
|
err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
|
|
omap_aes_get_res_pdev(dd, pdev, &res);
|
|
if (err)
|
|
goto err_res;
|
|
|
|
dd->io_base = devm_ioremap_resource(dev, &res);
|
|
if (IS_ERR(dd->io_base)) {
|
|
err = PTR_ERR(dd->io_base);
|
|
goto err_res;
|
|
}
|
|
dd->phys_base = res.start;
|
|
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
|
|
|
|
pm_runtime_enable(dev);
|
|
err = pm_runtime_get_sync(dev);
|
|
if (err < 0) {
|
|
dev_err(dev, "%s: failed to get_sync(%d)\n",
|
|
__func__, err);
|
|
goto err_res;
|
|
}
|
|
|
|
omap_aes_dma_stop(dd);
|
|
|
|
reg = omap_aes_read(dd, AES_REG_REV(dd));
|
|
|
|
pm_runtime_put_sync(dev);
|
|
|
|
dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
|
|
(reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
|
|
(reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
|
|
|
|
tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
|
|
|
|
err = omap_aes_dma_init(dd);
|
|
if (err == -EPROBE_DEFER) {
|
|
goto err_irq;
|
|
} else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
|
|
dd->pio_only = 1;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "can't get IRQ resource\n");
|
|
err = irq;
|
|
goto err_irq;
|
|
}
|
|
|
|
err = devm_request_irq(dev, irq, omap_aes_irq, 0,
|
|
dev_name(dev), dd);
|
|
if (err) {
|
|
dev_err(dev, "Unable to grab omap-aes IRQ\n");
|
|
goto err_irq;
|
|
}
|
|
}
|
|
|
|
spin_lock_init(&dd->lock);
|
|
|
|
INIT_LIST_HEAD(&dd->list);
|
|
spin_lock(&list_lock);
|
|
list_add_tail(&dd->list, &dev_list);
|
|
spin_unlock(&list_lock);
|
|
|
|
/* Initialize crypto engine */
|
|
dd->engine = crypto_engine_alloc_init(dev, 1);
|
|
if (!dd->engine) {
|
|
err = -ENOMEM;
|
|
goto err_engine;
|
|
}
|
|
|
|
err = crypto_engine_start(dd->engine);
|
|
if (err)
|
|
goto err_engine;
|
|
|
|
for (i = 0; i < dd->pdata->algs_info_size; i++) {
|
|
if (!dd->pdata->algs_info[i].registered) {
|
|
for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
|
|
algp = &dd->pdata->algs_info[i].algs_list[j];
|
|
|
|
pr_debug("reg alg: %s\n", algp->cra_name);
|
|
INIT_LIST_HEAD(&algp->cra_list);
|
|
|
|
err = crypto_register_alg(algp);
|
|
if (err)
|
|
goto err_algs;
|
|
|
|
dd->pdata->algs_info[i].registered++;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (dd->pdata->aead_algs_info &&
|
|
!dd->pdata->aead_algs_info->registered) {
|
|
for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
|
|
aalg = &dd->pdata->aead_algs_info->algs_list[i];
|
|
algp = &aalg->base;
|
|
|
|
pr_debug("reg alg: %s\n", algp->cra_name);
|
|
INIT_LIST_HEAD(&algp->cra_list);
|
|
|
|
err = crypto_register_aead(aalg);
|
|
if (err)
|
|
goto err_aead_algs;
|
|
|
|
dd->pdata->aead_algs_info->registered++;
|
|
}
|
|
}
|
|
|
|
err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
|
|
if (err) {
|
|
dev_err(dev, "could not create sysfs device attrs\n");
|
|
goto err_aead_algs;
|
|
}
|
|
|
|
return 0;
|
|
err_aead_algs:
|
|
for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
|
|
aalg = &dd->pdata->aead_algs_info->algs_list[i];
|
|
crypto_unregister_aead(aalg);
|
|
}
|
|
err_algs:
|
|
for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
|
|
for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
|
|
crypto_unregister_alg(
|
|
&dd->pdata->algs_info[i].algs_list[j]);
|
|
|
|
err_engine:
|
|
if (dd->engine)
|
|
crypto_engine_exit(dd->engine);
|
|
|
|
omap_aes_dma_cleanup(dd);
|
|
err_irq:
|
|
tasklet_kill(&dd->done_task);
|
|
pm_runtime_disable(dev);
|
|
err_res:
|
|
dd = NULL;
|
|
err_data:
|
|
dev_err(dev, "initialization failed.\n");
|
|
return err;
|
|
}
|
|
|
|
static int omap_aes_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_aes_dev *dd = platform_get_drvdata(pdev);
|
|
struct aead_alg *aalg;
|
|
int i, j;
|
|
|
|
if (!dd)
|
|
return -ENODEV;
|
|
|
|
spin_lock(&list_lock);
|
|
list_del(&dd->list);
|
|
spin_unlock(&list_lock);
|
|
|
|
for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
|
|
for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
|
|
crypto_unregister_alg(
|
|
&dd->pdata->algs_info[i].algs_list[j]);
|
|
|
|
for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) {
|
|
aalg = &dd->pdata->aead_algs_info->algs_list[i];
|
|
crypto_unregister_aead(aalg);
|
|
}
|
|
|
|
crypto_engine_exit(dd->engine);
|
|
|
|
tasklet_kill(&dd->done_task);
|
|
omap_aes_dma_cleanup(dd);
|
|
pm_runtime_disable(dd->dev);
|
|
dd = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int omap_aes_suspend(struct device *dev)
|
|
{
|
|
pm_runtime_put_sync(dev);
|
|
return 0;
|
|
}
|
|
|
|
static int omap_aes_resume(struct device *dev)
|
|
{
|
|
pm_runtime_get_sync(dev);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
|
|
|
|
static struct platform_driver omap_aes_driver = {
|
|
.probe = omap_aes_probe,
|
|
.remove = omap_aes_remove,
|
|
.driver = {
|
|
.name = "omap-aes",
|
|
.pm = &omap_aes_pm_ops,
|
|
.of_match_table = omap_aes_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(omap_aes_driver);
|
|
|
|
MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Dmitry Kasatkin");
|
|
|