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![Linus Walleij](/assets/img/avatar_default.png)
This driver is a pure GPIO driver and should only include <linux/gpio/driver.h>. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
419 lines
9.3 KiB
C
419 lines
9.3 KiB
C
/*
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* GPIO interface for IT87xx Super I/O chips
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*
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* Author: Diego Elio Pettenò <flameeyes@flameeyes.eu>
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* Copyright (c) 2017 Google, Inc.
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*
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* Based on it87_wdt.c by Oliver Schuster
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* gpio-it8761e.c by Denis Turischev
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* gpio-stmpe.c by Rabin Vincent
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/gpio/driver.h>
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/* Chip Id numbers */
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#define NO_DEV_ID 0xffff
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#define IT8620_ID 0x8620
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#define IT8628_ID 0x8628
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#define IT8728_ID 0x8728
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#define IT8732_ID 0x8732
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#define IT8761_ID 0x8761
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#define IT8772_ID 0x8772
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/* IO Ports */
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#define REG 0x2e
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#define VAL 0x2f
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/* Logical device Numbers LDN */
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#define GPIO 0x07
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/* Configuration Registers and Functions */
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#define LDNREG 0x07
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#define CHIPID 0x20
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#define CHIPREV 0x22
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/**
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* struct it87_gpio - it87-specific GPIO chip
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* @chip the underlying gpio_chip structure
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* @lock a lock to avoid races between operations
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* @io_base base address for gpio ports
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* @io_size size of the port rage starting from io_base.
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* @output_base Super I/O register address for Output Enable register
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* @simple_base Super I/O 'Simple I/O' Enable register
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* @simple_size Super IO 'Simple I/O' Enable register size; this is
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* required because IT87xx chips might only provide Simple I/O
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* switches on a subset of lines, whereas the others keep the
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* same status all time.
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*/
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struct it87_gpio {
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struct gpio_chip chip;
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spinlock_t lock;
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u16 io_base;
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u16 io_size;
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u8 output_base;
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u8 simple_base;
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u8 simple_size;
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};
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static struct it87_gpio it87_gpio_chip = {
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.lock = __SPIN_LOCK_UNLOCKED(it87_gpio_chip.lock),
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};
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/* Superio chip access functions; copied from wdt_it87 */
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static inline int superio_enter(void)
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{
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/*
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* Try to reserve REG and REG + 1 for exclusive access.
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*/
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if (!request_muxed_region(REG, 2, KBUILD_MODNAME))
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return -EBUSY;
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outb(0x87, REG);
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outb(0x01, REG);
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outb(0x55, REG);
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outb(0x55, REG);
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return 0;
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}
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static inline void superio_exit(void)
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{
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outb(0x02, REG);
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outb(0x02, VAL);
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release_region(REG, 2);
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}
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static inline void superio_select(int ldn)
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{
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outb(LDNREG, REG);
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outb(ldn, VAL);
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}
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static inline int superio_inb(int reg)
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{
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outb(reg, REG);
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return inb(VAL);
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}
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static inline void superio_outb(int val, int reg)
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{
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outb(reg, REG);
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outb(val, VAL);
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}
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static inline int superio_inw(int reg)
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{
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int val;
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outb(reg++, REG);
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val = inb(VAL) << 8;
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outb(reg, REG);
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val |= inb(VAL);
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return val;
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}
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static inline void superio_outw(int val, int reg)
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{
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outb(reg++, REG);
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outb(val >> 8, VAL);
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outb(reg, REG);
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outb(val, VAL);
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}
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static inline void superio_set_mask(int mask, int reg)
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{
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u8 curr_val = superio_inb(reg);
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u8 new_val = curr_val | mask;
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if (curr_val != new_val)
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superio_outb(new_val, reg);
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}
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static inline void superio_clear_mask(int mask, int reg)
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{
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u8 curr_val = superio_inb(reg);
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u8 new_val = curr_val & ~mask;
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if (curr_val != new_val)
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superio_outb(new_val, reg);
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}
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static int it87_gpio_request(struct gpio_chip *chip, unsigned gpio_num)
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{
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u8 mask, group;
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int rc = 0;
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struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
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mask = 1 << (gpio_num % 8);
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group = (gpio_num / 8);
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spin_lock(&it87_gpio->lock);
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rc = superio_enter();
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if (rc)
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goto exit;
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/* not all the IT87xx chips support Simple I/O and not all of
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* them allow all the lines to be set/unset to Simple I/O.
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*/
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if (group < it87_gpio->simple_size)
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superio_set_mask(mask, group + it87_gpio->simple_base);
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/* clear output enable, setting the pin to input, as all the
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* newly-exported GPIO interfaces are set to input.
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*/
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superio_clear_mask(mask, group + it87_gpio->output_base);
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superio_exit();
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exit:
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spin_unlock(&it87_gpio->lock);
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return rc;
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}
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static int it87_gpio_get(struct gpio_chip *chip, unsigned gpio_num)
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{
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u16 reg;
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u8 mask;
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struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
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mask = 1 << (gpio_num % 8);
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reg = (gpio_num / 8) + it87_gpio->io_base;
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return !!(inb(reg) & mask);
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}
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static int it87_gpio_direction_in(struct gpio_chip *chip, unsigned gpio_num)
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{
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u8 mask, group;
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int rc = 0;
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struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
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mask = 1 << (gpio_num % 8);
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group = (gpio_num / 8);
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spin_lock(&it87_gpio->lock);
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rc = superio_enter();
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if (rc)
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goto exit;
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/* clear the output enable bit */
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superio_clear_mask(mask, group + it87_gpio->output_base);
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superio_exit();
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exit:
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spin_unlock(&it87_gpio->lock);
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return rc;
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}
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static void it87_gpio_set(struct gpio_chip *chip,
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unsigned gpio_num, int val)
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{
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u8 mask, curr_vals;
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u16 reg;
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struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
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mask = 1 << (gpio_num % 8);
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reg = (gpio_num / 8) + it87_gpio->io_base;
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curr_vals = inb(reg);
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if (val)
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outb(curr_vals | mask, reg);
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else
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outb(curr_vals & ~mask, reg);
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}
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static int it87_gpio_direction_out(struct gpio_chip *chip,
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unsigned gpio_num, int val)
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{
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u8 mask, group;
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int rc = 0;
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struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
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mask = 1 << (gpio_num % 8);
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group = (gpio_num / 8);
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spin_lock(&it87_gpio->lock);
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rc = superio_enter();
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if (rc)
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goto exit;
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/* set the output enable bit */
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superio_set_mask(mask, group + it87_gpio->output_base);
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it87_gpio_set(chip, gpio_num, val);
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superio_exit();
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exit:
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spin_unlock(&it87_gpio->lock);
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return rc;
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}
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static const struct gpio_chip it87_template_chip = {
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.label = KBUILD_MODNAME,
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.owner = THIS_MODULE,
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.request = it87_gpio_request,
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.get = it87_gpio_get,
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.direction_input = it87_gpio_direction_in,
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.set = it87_gpio_set,
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.direction_output = it87_gpio_direction_out,
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.base = -1
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};
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static int __init it87_gpio_init(void)
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{
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int rc = 0, i;
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u16 chip_type;
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u8 chip_rev, gpio_ba_reg;
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char *labels, **labels_table;
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struct it87_gpio *it87_gpio = &it87_gpio_chip;
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rc = superio_enter();
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if (rc)
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return rc;
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chip_type = superio_inw(CHIPID);
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chip_rev = superio_inb(CHIPREV) & 0x0f;
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superio_exit();
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it87_gpio->chip = it87_template_chip;
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switch (chip_type) {
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case IT8620_ID:
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case IT8628_ID:
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gpio_ba_reg = 0x62;
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it87_gpio->io_size = 11;
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it87_gpio->output_base = 0xc8;
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it87_gpio->simple_size = 0;
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it87_gpio->chip.ngpio = 64;
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break;
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case IT8728_ID:
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case IT8732_ID:
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case IT8772_ID:
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gpio_ba_reg = 0x62;
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it87_gpio->io_size = 8;
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it87_gpio->output_base = 0xc8;
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it87_gpio->simple_base = 0xc0;
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it87_gpio->simple_size = 5;
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it87_gpio->chip.ngpio = 64;
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break;
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case IT8761_ID:
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gpio_ba_reg = 0x60;
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it87_gpio->io_size = 4;
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it87_gpio->output_base = 0xf0;
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it87_gpio->simple_size = 0;
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it87_gpio->chip.ngpio = 16;
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break;
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case NO_DEV_ID:
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pr_err("no device\n");
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return -ENODEV;
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default:
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pr_err("Unknown Chip found, Chip %04x Revision %x\n",
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chip_type, chip_rev);
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return -ENODEV;
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}
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rc = superio_enter();
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if (rc)
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return rc;
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superio_select(GPIO);
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/* fetch GPIO base address */
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it87_gpio->io_base = superio_inw(gpio_ba_reg);
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superio_exit();
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pr_info("Found Chip IT%04x rev %x. %u GPIO lines starting at %04xh\n",
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chip_type, chip_rev, it87_gpio->chip.ngpio,
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it87_gpio->io_base);
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if (!request_region(it87_gpio->io_base, it87_gpio->io_size,
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KBUILD_MODNAME))
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return -EBUSY;
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/* Set up aliases for the GPIO connection.
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*
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* ITE documentation for recent chips such as the IT8728F
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* refers to the GPIO lines as GPxy, with a coordinates system
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* where x is the GPIO group (starting from 1) and y is the
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* bit within the group.
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*
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* By creating these aliases, we make it easier to understand
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* to which GPIO pin we're referring to.
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*/
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labels = kcalloc(it87_gpio->chip.ngpio, sizeof("it87_gpXY"),
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GFP_KERNEL);
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labels_table = kcalloc(it87_gpio->chip.ngpio, sizeof(const char *),
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GFP_KERNEL);
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if (!labels || !labels_table) {
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rc = -ENOMEM;
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goto labels_free;
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}
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for (i = 0; i < it87_gpio->chip.ngpio; i++) {
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char *label = &labels[i * sizeof("it87_gpXY")];
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sprintf(label, "it87_gp%u%u", 1+(i/8), i%8);
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labels_table[i] = label;
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}
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it87_gpio->chip.names = (const char *const*)labels_table;
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rc = gpiochip_add_data(&it87_gpio->chip, it87_gpio);
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if (rc)
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goto labels_free;
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return 0;
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labels_free:
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kfree(labels_table);
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kfree(labels);
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release_region(it87_gpio->io_base, it87_gpio->io_size);
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return rc;
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}
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static void __exit it87_gpio_exit(void)
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{
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struct it87_gpio *it87_gpio = &it87_gpio_chip;
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gpiochip_remove(&it87_gpio->chip);
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release_region(it87_gpio->io_base, it87_gpio->io_size);
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kfree(it87_gpio->chip.names[0]);
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kfree(it87_gpio->chip.names);
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}
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module_init(it87_gpio_init);
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module_exit(it87_gpio_exit);
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MODULE_AUTHOR("Diego Elio Pettenò <flameeyes@flameeyes.eu>");
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MODULE_DESCRIPTION("GPIO interface for IT87xx Super I/O chips");
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MODULE_LICENSE("GPL");
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