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![Jan Beulich](/assets/img/avatar_default.png)
Candidate memory ranges were not calculated properly (start addresses got needlessly rounded down, and end addresses didn't get rounded up at all), address comparison for secondary CPUs was done on only part of the address, and disabled status wasn't tracked properly. Signed-off-by: Jan Beulich <jbeulich@novell.com> Acked-by: Yinghai Lu <yinghai@kernel.org> Acked-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <4CE24DF40200007800022737@vpn.id2.novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
237 lines
5.4 KiB
C
237 lines
5.4 KiB
C
/*
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* AMD Family 10h mmconfig enablement
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/dmi.h>
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#include <linux/range.h>
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#include <asm/pci-direct.h>
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#include <linux/sort.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/acpi.h>
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#include <asm/mmconfig.h>
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#include <asm/pci_x86.h>
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struct pci_hostbridge_probe {
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u32 bus;
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u32 slot;
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u32 vendor;
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u32 device;
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};
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static u64 __cpuinitdata fam10h_pci_mmconf_base;
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static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
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{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
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};
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static int __cpuinit cmp_range(const void *x1, const void *x2)
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{
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const struct range *r1 = x1;
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const struct range *r2 = x2;
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int start1, start2;
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start1 = r1->start >> 32;
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start2 = r2->start >> 32;
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return start1 - start2;
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}
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#define MMCONF_UNIT (1ULL << FAM10H_MMIO_CONF_BASE_SHIFT)
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#define MMCONF_MASK (~(MMCONF_UNIT - 1))
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#define MMCONF_SIZE (MMCONF_UNIT << 8)
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/* need to avoid (0xfd<<32), (0xfe<<32), and (0xff<<32), ht used space */
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#define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
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#define BASE_VALID(b) ((b) + MMCONF_SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
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static void __cpuinit get_fam10h_pci_mmconf_base(void)
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{
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int i;
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unsigned bus;
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unsigned slot;
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int found;
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u64 val;
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u32 address;
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u64 tom2;
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u64 base = FAM10H_PCI_MMCONF_BASE;
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int hi_mmio_num;
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struct range range[8];
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/* only try to get setting from BSP */
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if (fam10h_pci_mmconf_base)
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return;
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if (!early_pci_allowed())
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return;
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found = 0;
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for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
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u32 id;
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u16 device;
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u16 vendor;
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bus = pci_probes[i].bus;
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slot = pci_probes[i].slot;
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id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
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vendor = id & 0xffff;
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device = (id>>16) & 0xffff;
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if (pci_probes[i].vendor == vendor &&
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pci_probes[i].device == device) {
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found = 1;
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break;
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}
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}
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if (!found)
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return;
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/* SYS_CFG */
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address = MSR_K8_SYSCFG;
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rdmsrl(address, val);
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/* TOP_MEM2 is not enabled? */
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if (!(val & (1<<21))) {
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tom2 = 1ULL << 32;
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} else {
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/* TOP_MEM2 */
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address = MSR_K8_TOP_MEM2;
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rdmsrl(address, val);
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tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
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}
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if (base <= tom2)
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base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK;
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/*
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* need to check if the range is in the high mmio range that is
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* above 4G
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*/
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hi_mmio_num = 0;
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for (i = 0; i < 8; i++) {
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u32 reg;
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u64 start;
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u64 end;
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reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
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if (!(reg & 3))
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continue;
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start = (u64)(reg & 0xffffff00) << 8; /* 39:16 on 31:8*/
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reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
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end = ((u64)(reg & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/
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if (end < tom2)
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continue;
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range[hi_mmio_num].start = start;
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range[hi_mmio_num].end = end;
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hi_mmio_num++;
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}
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if (!hi_mmio_num)
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goto out;
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/* sort the range */
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sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
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if (range[hi_mmio_num - 1].end < base)
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goto out;
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if (range[0].start > base + MMCONF_SIZE)
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goto out;
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/* need to find one window */
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base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT;
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if ((base > tom2) && BASE_VALID(base))
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goto out;
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base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK;
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if (BASE_VALID(base))
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goto out;
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/* need to find window between ranges */
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for (i = 1; i < hi_mmio_num; i++) {
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base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK;
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val = range[i].start & MMCONF_MASK;
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if (val >= base + MMCONF_SIZE && BASE_VALID(base))
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goto out;
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}
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return;
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out:
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fam10h_pci_mmconf_base = base;
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}
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void __cpuinit fam10h_check_enable_mmcfg(void)
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{
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u64 val;
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u32 address;
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if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
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return;
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address = MSR_FAM10H_MMIO_CONF_BASE;
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rdmsrl(address, val);
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/* try to make sure that AP's setting is identical to BSP setting */
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if (val & FAM10H_MMIO_CONF_ENABLE) {
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unsigned busnbits;
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busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
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FAM10H_MMIO_CONF_BUSRANGE_MASK;
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/* only trust the one handle 256 buses, if acpi=off */
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if (!acpi_pci_disabled || busnbits >= 8) {
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u64 base = val & MMCONF_MASK;
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if (!fam10h_pci_mmconf_base) {
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fam10h_pci_mmconf_base = base;
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return;
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} else if (fam10h_pci_mmconf_base == base)
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return;
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}
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}
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/*
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* if it is not enabled, try to enable it and assume only one segment
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* with 256 buses
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*/
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get_fam10h_pci_mmconf_base();
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if (!fam10h_pci_mmconf_base) {
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pci_probe &= ~PCI_CHECK_ENABLE_AMD_MMCONF;
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return;
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}
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printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
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val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
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(FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
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val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
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FAM10H_MMIO_CONF_ENABLE;
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wrmsrl(address, val);
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}
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static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
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{
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pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
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return 0;
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}
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static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
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{
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.callback = set_check_enable_amd_mmconf,
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.ident = "Sun Microsystems Machine",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
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},
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},
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{}
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};
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/* Called from a __cpuinit function, but only on the BSP. */
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void __ref check_enable_amd_mmconf_dmi(void)
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{
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dmi_check_system(mmconf_dmi_table);
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}
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