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![Shengjiu Wang](/assets/img/avatar_default.png)
The AUD2HTX is a digital module that provides a bridge between the Audio Subsystem and the HDMI RTX Subsystem. This module includes intermediate storage to queue SDMA transactions prior to being synchronized and passed to the HDMI RTX Subsystem over the Audio Link. The AUD2HTX contains a DMA request routed to the SDMA module. This DMA request is controlled based on the watermark level in the 32-entry sample buffer. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1604281947-26874-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2020 NXP
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*/
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#ifndef _FSL_AUD2HTX_H
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#define _FSL_AUD2HTX_H
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#define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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/* AUD2HTX Register Map */
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#define AUD2HTX_CTRL 0x0 /* AUD2HTX Control Register */
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#define AUD2HTX_CTRL_EXT 0x4 /* AUD2HTX Control Extended Register */
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#define AUD2HTX_WR 0x8 /* AUD2HTX Write Register */
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#define AUD2HTX_STATUS 0xC /* AUD2HTX Status Register */
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#define AUD2HTX_IRQ_NOMASK 0x10 /* AUD2HTX Nonmasked Interrupt Flags Register */
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#define AUD2HTX_IRQ_MASKED 0x14 /* AUD2HTX Masked Interrupt Flags Register */
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#define AUD2HTX_IRQ_MASK 0x18 /* AUD2HTX IRQ Masks Register */
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/* AUD2HTX Control Register */
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#define AUD2HTX_CTRL_EN BIT(0)
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/* AUD2HTX Control Extended Register */
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#define AUD2HTX_CTRE_DE BIT(0)
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#define AUD2HTX_CTRE_DT_SHIFT 0x1
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#define AUD2HTX_CTRE_DT_WIDTH 0x2
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#define AUD2HTX_CTRE_DT_MASK ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \
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<< AUD2HTX_CTRE_DT_SHIFT)
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#define AUD2HTX_CTRE_WL_SHIFT 16
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#define AUD2HTX_CTRE_WL_WIDTH 5
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#define AUD2HTX_CTRE_WL_MASK ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \
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<< AUD2HTX_CTRE_WL_SHIFT)
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#define AUD2HTX_CTRE_WH_SHIFT 24
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#define AUD2HTX_CTRE_WH_WIDTH 5
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#define AUD2HTX_CTRE_WH_MASK ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \
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<< AUD2HTX_CTRE_WH_SHIFT)
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/* AUD2HTX IRQ Masks Register */
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#define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2)
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#define AUD2HTX_WM_LOW_IRQ_MASK BIT(1)
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#define AUD2HTX_OVF_MASK BIT(0)
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#define AUD2HTX_FIFO_DEPTH 0x20
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#define AUD2HTX_WTMK_LOW 0x10
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#define AUD2HTX_WTMK_HIGH 0x10
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#define AUD2HTX_MAXBURST 0x10
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/**
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* fsl_aud2htx: AUD2HTX private data
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*
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* @pdev: platform device pointer
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* @regmap: regmap handler
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* @bus_clk: clock source to access register
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* @dma_params_rx: DMA parameters for receive channel
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* @dma_params_tx: DMA parameters for transmit channel
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*/
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struct fsl_aud2htx {
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struct platform_device *pdev;
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struct regmap *regmap;
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struct clk *bus_clk;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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};
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#endif /* _FSL_AUD2HTX_H */
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