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e765886249
Tegra audio graph card has many DAI links which connects internal
AHUB modules and external audio codecs. Since these are DPCM links,
hw_params() call in the machine driver happens for each connected
BE link and PLLA is updated every time. This is not really needed
for all links as only I/O link DAIs derive respective clocks from
PLLA_OUT0 and thus from PLLA. Hence add checks to limit the clock
updates to DAIs over I/O links.
This found to be fixing a DMIC clock discrepancy which is suspected
to happen because of back to back quick PLLA and PLLA_OUT0 rate
updates. This was observed on Jetson TX2 platform where DMIC clock
ended up with unexpected value.
Fixes:
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.. | ||
Kconfig | ||
Makefile | ||
tegra20_ac97.c | ||
tegra20_ac97.h | ||
tegra20_das.c | ||
tegra20_i2s.c | ||
tegra20_i2s.h | ||
tegra20_spdif.c | ||
tegra20_spdif.h | ||
tegra30_ahub.c | ||
tegra30_ahub.h | ||
tegra30_i2s.c | ||
tegra30_i2s.h | ||
tegra186_asrc.c | ||
tegra186_asrc.h | ||
tegra186_dspk.c | ||
tegra186_dspk.h | ||
tegra210_admaif.c | ||
tegra210_admaif.h | ||
tegra210_adx.c | ||
tegra210_adx.h | ||
tegra210_ahub.c | ||
tegra210_ahub.h | ||
tegra210_amx.c | ||
tegra210_amx.h | ||
tegra210_dmic.c | ||
tegra210_dmic.h | ||
tegra210_i2s.c | ||
tegra210_i2s.h | ||
tegra210_mbdrc.c | ||
tegra210_mbdrc.h | ||
tegra210_mixer.c | ||
tegra210_mixer.h | ||
tegra210_mvc.c | ||
tegra210_mvc.h | ||
tegra210_ope.c | ||
tegra210_ope.h | ||
tegra210_peq.c | ||
tegra210_peq.h | ||
tegra210_sfc.c | ||
tegra210_sfc.h | ||
tegra_asoc_machine.c | ||
tegra_asoc_machine.h | ||
tegra_audio_graph_card.c | ||
tegra_cif.h | ||
tegra_pcm.c | ||
tegra_pcm.h | ||
tegra_wm8903.c |