linux-stable/drivers/clk/ux500
Maxime Ripard b7f0dee221 clk: ux500: sysctrl: Add a determine_rate hook
The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent
hook, but doesn't provide a determine_rate implementation.

This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidates to
trigger that parent change are either the assigned-clock-parents device
tree property or a call to clk_set_rate(), with determine_rate()
figuring out which parent is the best suited for a given rate.

The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.

Similarly, it doesn't look like the device tree using that clock driver
uses any of the assigned-clock properties on that clock.

So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().

The latter case would be equivalent to setting the determine_rate
implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no
determine_rate implementation is provided, clk_round_rate() (through
clk_core_round_rate_nolock()) will call itself on the parent if
CLK_SET_RATE_PARENT is set, and will not change the clock rate
otherwise.

And if it was an oversight, then we are at least explicit about our
behavior now and it can be further refined down the line.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-38-971d5077e7d2@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-06-08 18:39:30 -07:00
..
Makefile clk: ux500: Add driver for the reset portions of PRCC 2021-10-26 18:06:05 -07:00
abx500-clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194 2019-05-30 11:29:22 -07:00
clk-prcc.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194 2019-05-30 11:29:22 -07:00
clk-prcmu.c clk: ux500: prcmu: Add a determine_rate hook 2023-06-08 18:39:30 -07:00
clk-sysctrl.c clk: ux500: sysctrl: Add a determine_rate hook 2023-06-08 18:39:30 -07:00
clk.h clk: ux500: Implement the missing CLKOUT clocks 2022-04-25 16:17:25 -07:00
prcc.h clk: ux500: Add driver for the reset portions of PRCC 2021-10-26 18:06:05 -07:00
reset-prcc.c clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base() 2022-05-18 13:34:03 -07:00
reset-prcc.h clk: ux500: Add driver for the reset portions of PRCC 2021-10-26 18:06:05 -07:00
u8500_of_clk.c clk: ux500: Implement the missing CLKOUT clocks 2022-04-25 16:17:25 -07:00