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09af39f649
xtensa core may be configured without register windows support, don't use register window specific opcodes in that case. Use window register specific opcodes to initialize hardware or reset core to a known state regardless of the chosen ABI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
79 lines
1.4 KiB
ArmAsm
79 lines
1.4 KiB
ArmAsm
/*
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* arch/xtensa/boot/boot-elf/bootstrap.S
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*
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* Low-level exception handling
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004 - 2013 by Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier <marc@tensilica.com>
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* Piet Delaney <piet@tensilica.com>
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*/
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#include <asm/bootparam.h>
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#include <asm/initialize_mmu.h>
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#include <asm/vectors.h>
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#include <linux/linkage.h>
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.section .ResetVector.text, "ax"
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.global _ResetVector
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.global reset
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_ResetVector:
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_j _SetupMMU
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.begin no-absolute-literals
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.literal_position
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#ifdef CONFIG_PARSE_BOOTPARAM
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.align 4
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_bootparam:
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.short BP_TAG_FIRST
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.short 4
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.long BP_VERSION
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.short BP_TAG_LAST
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.short 0
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.long 0
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#endif
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.align 4
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_SetupMMU:
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#if XCHAL_HAVE_WINDOWED
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movi a0, 0
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wsr a0, windowbase
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rsync
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movi a0, 1
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wsr a0, windowstart
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rsync
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#endif
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movi a0, 0x1F
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wsr a0, ps
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rsync
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#ifndef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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initialize_mmu
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#endif
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rsil a0, XCHAL_DEBUGLEVEL-1
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rsync
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reset:
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#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \
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XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
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movi a0, CONFIG_KERNEL_LOAD_ADDRESS
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#else
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movi a0, KERNELOFFSET
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#endif
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#ifdef CONFIG_PARSE_BOOTPARAM
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movi a2, _bootparam
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#else
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movi a2, 0
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#endif
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movi a3, 0
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movi a4, 0
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jx a0
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.end no-absolute-literals
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