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c61cfb941d
Finally the code handles the IPA memory region array in the configuration data without assuming it is indexed by region ID. Get rid of the array index designators where these arrays are initialized. As a result, there's no more need to define an explicitly undefined memory region ID, so get rid of that. Change ipa_mem_find() so it no longer assumes the ipa->mem[] array is indexed by memory region ID. Instead, have it search the array for the entry having the requested memory ID, and return the address of the descriptor if found. Otherwise return NULL. Stop allowing memory regions to be defined with zero size and zero canary value. Check for this condition in ipa_mem_valid_one(). As a result, it is not necessary to check for this case in ipa_mem_config(). Finally, there is no need for IPA_MEM_UNDEFINED to be defined any more, so get rid of it. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
380 lines
8.4 KiB
C
380 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2019-2021 Linaro Ltd. */
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#include <linux/log2.h>
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#include "gsi.h"
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#include "ipa_data.h"
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#include "ipa_endpoint.h"
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#include "ipa_mem.h"
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/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.2 */
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enum ipa_resource_type {
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/* Source resource types; first must have value 0 */
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IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
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IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
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IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
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/* Destination resource types; first must have value 0 */
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IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
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IPA_RESOURCE_TYPE_DST_DPS_DMARS,
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};
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/* Resource groups used for an SoC having IPA v4.2 */
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enum ipa_rsrc_group_id {
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/* Source resource group identifiers */
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IPA_RSRC_GROUP_SRC_UL_DL = 0,
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IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
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/* Destination resource group identifiers */
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IPA_RSRC_GROUP_DST_UL_DL_DPL = 0,
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IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
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};
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/* QSB configuration data for an SoC having IPA v4.2 */
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static const struct ipa_qsb_data ipa_qsb_data[] = {
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[IPA_QSB_MASTER_DDR] = {
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.max_writes = 8,
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.max_reads = 12,
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/* no outstanding read byte (beat) limit */
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},
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};
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/* Endpoint configuration data for an SoC having IPA v4.2 */
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static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
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[IPA_ENDPOINT_AP_COMMAND_TX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 1,
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.endpoint_id = 6,
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.toward_ipa = true,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 20,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
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.dma_mode = true,
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.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
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.tx = {
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.seq_type = IPA_SEQ_DMA,
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_LAN_RX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 2,
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.endpoint_id = 8,
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.toward_ipa = false,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 6,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
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.aggregation = true,
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.status_enable = true,
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.rx = {
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.pad_align = ilog2(sizeof(u32)),
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_MODEM_TX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 0,
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.endpoint_id = 1,
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.toward_ipa = true,
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.channel = {
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.tre_count = 512,
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.event_count = 512,
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.tlv_count = 8,
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},
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.endpoint = {
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.filter_support = true,
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.config = {
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.resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
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.checksum = true,
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.qmap = true,
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.status_enable = true,
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.tx = {
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.seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC,
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.seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
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.status_endpoint =
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IPA_ENDPOINT_MODEM_AP_RX,
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_MODEM_RX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 3,
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.endpoint_id = 9,
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.toward_ipa = false,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 6,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
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.checksum = true,
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.qmap = true,
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.aggregation = true,
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.rx = {
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.aggr_close_eof = true,
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},
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},
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},
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},
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[IPA_ENDPOINT_MODEM_COMMAND_TX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 1,
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.endpoint_id = 5,
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.toward_ipa = true,
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},
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[IPA_ENDPOINT_MODEM_LAN_RX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 3,
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.endpoint_id = 11,
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.toward_ipa = false,
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},
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[IPA_ENDPOINT_MODEM_AP_TX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 0,
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.endpoint_id = 4,
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.toward_ipa = true,
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.endpoint = {
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.filter_support = true,
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},
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},
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[IPA_ENDPOINT_MODEM_AP_RX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 2,
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.endpoint_id = 10,
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.toward_ipa = false,
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},
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};
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/* Source resource configuration data for an SoC having IPA v4.2 */
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static const struct ipa_resource ipa_resource_src[] = {
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[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 3, .max = 63,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 3, .max = 3,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 10, .max = 10,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 1, .max = 1,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 5, .max = 5,
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},
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},
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};
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/* Destination resource configuration data for an SoC having IPA v4.2 */
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static const struct ipa_resource ipa_resource_dst[] = {
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[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
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.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
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.min = 3, .max = 3,
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},
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},
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[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
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.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
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.min = 1, .max = 63,
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},
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},
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};
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/* Resource configuration data for an SoC having IPA v4.2 */
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static const struct ipa_resource_data ipa_resource_data = {
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.rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
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.rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
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.resource_src_count = ARRAY_SIZE(ipa_resource_src),
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.resource_src = ipa_resource_src,
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.resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
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.resource_dst = ipa_resource_dst,
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};
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/* IPA-resident memory region data for an SoC having IPA v4.2 */
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static const struct ipa_mem ipa_mem_local_data[] = {
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{
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.id = IPA_MEM_UC_SHARED,
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.offset = 0x0000,
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.size = 0x0080,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_UC_INFO,
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.offset = 0x0080,
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.size = 0x0200,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_V4_FILTER_HASHED,
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.offset = 0x0288,
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.size = 0,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V4_FILTER,
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.offset = 0x0290,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_FILTER_HASHED,
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.offset = 0x0310,
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.size = 0,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_FILTER,
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.offset = 0x0318,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V4_ROUTE_HASHED,
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.offset = 0x0398,
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.size = 0,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V4_ROUTE,
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.offset = 0x03a0,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_ROUTE_HASHED,
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.offset = 0x0420,
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.size = 0,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_V6_ROUTE,
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.offset = 0x0428,
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.size = 0x0078,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_MODEM_HEADER,
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.offset = 0x04a8,
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.size = 0x0140,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_MODEM_PROC_CTX,
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.offset = 0x05f0,
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.size = 0x0200,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_AP_PROC_CTX,
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.offset = 0x07f0,
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.size = 0x0200,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_PDN_CONFIG,
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.offset = 0x09f8,
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.size = 0x0050,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_STATS_QUOTA_MODEM,
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.offset = 0x0a50,
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.size = 0x0060,
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.canary_count = 2,
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},
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{
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.id = IPA_MEM_STATS_TETHERING,
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.offset = 0x0ab0,
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.size = 0x0140,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_MODEM,
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.offset = 0x0bf0,
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.size = 0x140c,
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.canary_count = 0,
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},
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{
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.id = IPA_MEM_END_MARKER,
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.offset = 0x2000,
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.size = 0,
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.canary_count = 1,
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},
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};
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/* Memory configuration data for an SoC having IPA v4.2 */
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static const struct ipa_mem_data ipa_mem_data = {
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.local_count = ARRAY_SIZE(ipa_mem_local_data),
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.local = ipa_mem_local_data,
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.imem_addr = 0x146a8000,
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.imem_size = 0x00002000,
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.smem_id = 497,
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.smem_size = 0x00002000,
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};
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/* Interconnect rates are in 1000 byte/second units */
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static const struct ipa_interconnect_data ipa_interconnect_data[] = {
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{
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.name = "memory",
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.peak_bandwidth = 465000, /* 465 MBps */
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.average_bandwidth = 80000, /* 80 MBps */
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},
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/* Average bandwidth is unused for the next two interconnects */
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{
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.name = "imem",
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.peak_bandwidth = 68570, /* 68.570 MBps */
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.average_bandwidth = 0, /* unused */
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},
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{
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.name = "config",
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.peak_bandwidth = 30000, /* 30 MBps */
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.average_bandwidth = 0, /* unused */
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},
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};
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/* Clock and interconnect configuration data for an SoC having IPA v4.2 */
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static const struct ipa_clock_data ipa_clock_data = {
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.core_clock_rate = 100 * 1000 * 1000, /* Hz */
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.interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
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.interconnect_data = ipa_interconnect_data,
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};
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/* Configuration data for an SoC having IPA v4.2 */
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const struct ipa_data ipa_data_v4_2 = {
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.version = IPA_VERSION_4_2,
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/* backward_compat value is 0 */
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.qsb_count = ARRAY_SIZE(ipa_qsb_data),
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.qsb_data = ipa_qsb_data,
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.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
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.endpoint_data = ipa_gsi_endpoint_data,
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.resource_data = &ipa_resource_data,
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.mem_data = &ipa_mem_data,
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.clock_data = &ipa_clock_data,
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};
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