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![Yang Yingliang](/assets/img/avatar_default.png)
Use devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
208 lines
5.1 KiB
C
208 lines
5.1 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Driver for the MDIO interface of Microsemi network switches.
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*
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* Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_mdio.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#define MSCC_MIIM_REG_STATUS 0x0
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#define MSCC_MIIM_STATUS_STAT_PENDING BIT(2)
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#define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
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#define MSCC_MIIM_REG_CMD 0x8
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#define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
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#define MSCC_MIIM_CMD_OPR_READ BIT(2)
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#define MSCC_MIIM_CMD_WRDATA_SHIFT 4
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#define MSCC_MIIM_CMD_REGAD_SHIFT 20
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#define MSCC_MIIM_CMD_PHYAD_SHIFT 25
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#define MSCC_MIIM_CMD_VLD BIT(31)
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#define MSCC_MIIM_REG_DATA 0xC
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#define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
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#define MSCC_PHY_REG_PHY_CFG 0x0
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#define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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#define PHY_CFG_PHY_COMMON_RESET BIT(4)
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#define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
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#define MSCC_PHY_REG_PHY_STATUS 0x4
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struct mscc_miim_dev {
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void __iomem *regs;
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void __iomem *phy_regs;
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};
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/* When high resolution timers aren't built-in: we can't use usleep_range() as
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* we would sleep way too long. Use udelay() instead.
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*/
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#define mscc_readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \
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({ \
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if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \
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readl_poll_timeout_atomic(addr, val, cond, delay_us, \
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timeout_us); \
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readl_poll_timeout(addr, val, cond, delay_us, timeout_us); \
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})
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static int mscc_miim_wait_ready(struct mii_bus *bus)
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{
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struct mscc_miim_dev *miim = bus->priv;
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u32 val;
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return mscc_readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val,
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!(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
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10000);
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}
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static int mscc_miim_wait_pending(struct mii_bus *bus)
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{
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struct mscc_miim_dev *miim = bus->priv;
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u32 val;
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return mscc_readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val,
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!(val & MSCC_MIIM_STATUS_STAT_PENDING),
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50, 10000);
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}
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static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct mscc_miim_dev *miim = bus->priv;
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u32 val;
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int ret;
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ret = mscc_miim_wait_pending(bus);
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if (ret)
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goto out;
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writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
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(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ,
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miim->regs + MSCC_MIIM_REG_CMD);
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ret = mscc_miim_wait_ready(bus);
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if (ret)
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goto out;
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val = readl(miim->regs + MSCC_MIIM_REG_DATA);
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if (val & MSCC_MIIM_DATA_ERROR) {
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ret = -EIO;
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goto out;
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}
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ret = val & 0xFFFF;
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out:
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return ret;
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}
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static int mscc_miim_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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struct mscc_miim_dev *miim = bus->priv;
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int ret;
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ret = mscc_miim_wait_pending(bus);
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if (ret < 0)
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goto out;
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writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
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(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
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(value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
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MSCC_MIIM_CMD_OPR_WRITE,
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miim->regs + MSCC_MIIM_REG_CMD);
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out:
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return ret;
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}
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static int mscc_miim_reset(struct mii_bus *bus)
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{
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struct mscc_miim_dev *miim = bus->priv;
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if (miim->phy_regs) {
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writel(0, miim->phy_regs + MSCC_PHY_REG_PHY_CFG);
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writel(0x1ff, miim->phy_regs + MSCC_PHY_REG_PHY_CFG);
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mdelay(500);
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}
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return 0;
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}
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static int mscc_miim_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct mii_bus *bus;
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struct mscc_miim_dev *dev;
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int ret;
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bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*dev));
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if (!bus)
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return -ENOMEM;
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bus->name = "mscc_miim";
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bus->read = mscc_miim_read;
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bus->write = mscc_miim_write;
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bus->reset = mscc_miim_reset;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
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bus->parent = &pdev->dev;
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dev = bus->priv;
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dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(dev->regs)) {
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dev_err(&pdev->dev, "Unable to map MIIM registers\n");
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return PTR_ERR(dev->regs);
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (res) {
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dev->phy_regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(dev->phy_regs)) {
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dev_err(&pdev->dev, "Unable to map internal phy registers\n");
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return PTR_ERR(dev->phy_regs);
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}
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}
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ret = of_mdiobus_register(bus, pdev->dev.of_node);
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if (ret < 0) {
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dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, bus);
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return 0;
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}
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static int mscc_miim_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = platform_get_drvdata(pdev);
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mdiobus_unregister(bus);
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return 0;
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}
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static const struct of_device_id mscc_miim_match[] = {
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{ .compatible = "mscc,ocelot-miim" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mscc_miim_match);
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static struct platform_driver mscc_miim_driver = {
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.probe = mscc_miim_probe,
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.remove = mscc_miim_remove,
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.driver = {
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.name = "mscc-miim",
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.of_match_table = mscc_miim_match,
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},
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};
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module_platform_driver(mscc_miim_driver);
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MODULE_DESCRIPTION("Microsemi MIIM driver");
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MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
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MODULE_LICENSE("Dual MIT/GPL");
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