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![Ioana Ciornei](/assets/img/avatar_default.png)
In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Marek Vasut <marex@denx.de> Cc: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
827 lines
20 KiB
C
827 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* NXP TJA1100 BroadRReach PHY driver
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*
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* Copyright (C) 2018 Marek Vasut <marex@denx.de>
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*/
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#include <linux/delay.h>
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#include <linux/ethtool.h>
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#include <linux/ethtool_netlink.h>
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#include <linux/kernel.h>
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#include <linux/mdio.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/hwmon.h>
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#include <linux/bitfield.h>
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#include <linux/of_mdio.h>
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#include <linux/of_irq.h>
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#define PHY_ID_MASK 0xfffffff0
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#define PHY_ID_TJA1100 0x0180dc40
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#define PHY_ID_TJA1101 0x0180dd00
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#define PHY_ID_TJA1102 0x0180dc80
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#define MII_ECTRL 17
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#define MII_ECTRL_LINK_CONTROL BIT(15)
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#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
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#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
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#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
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#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
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#define MII_ECTRL_CABLE_TEST BIT(5)
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#define MII_ECTRL_CONFIG_EN BIT(2)
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#define MII_ECTRL_WAKE_REQUEST BIT(0)
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#define MII_CFG1 18
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#define MII_CFG1_MASTER_SLAVE BIT(15)
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#define MII_CFG1_AUTO_OP BIT(14)
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#define MII_CFG1_SLEEP_CONFIRM BIT(6)
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#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
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#define MII_CFG1_LED_MODE_LINKUP 0
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#define MII_CFG1_LED_ENABLE BIT(3)
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#define MII_CFG2 19
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#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
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#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
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#define MII_INTSRC 21
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#define MII_INTSRC_LINK_FAIL BIT(10)
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#define MII_INTSRC_LINK_UP BIT(9)
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#define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
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#define MII_INTSRC_TEMP_ERR BIT(1)
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#define MII_INTSRC_UV_ERR BIT(3)
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#define MII_INTEN 22
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#define MII_INTEN_LINK_FAIL BIT(10)
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#define MII_INTEN_LINK_UP BIT(9)
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#define MII_COMMSTAT 23
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#define MII_COMMSTAT_LINK_UP BIT(15)
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#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
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#define MII_COMMSTAT_SQI_MAX 7
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#define MII_GENSTAT 24
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#define MII_GENSTAT_PLL_LOCKED BIT(14)
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#define MII_EXTSTAT 25
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#define MII_EXTSTAT_SHORT_DETECT BIT(8)
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#define MII_EXTSTAT_OPEN_DETECT BIT(7)
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#define MII_EXTSTAT_POLARITY_DETECT BIT(6)
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#define MII_COMMCFG 27
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#define MII_COMMCFG_AUTO_OP BIT(15)
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struct tja11xx_priv {
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char *hwmon_name;
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struct device *hwmon_dev;
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struct phy_device *phydev;
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struct work_struct phy_register_work;
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};
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struct tja11xx_phy_stats {
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const char *string;
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u8 reg;
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u8 off;
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u16 mask;
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};
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static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
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{ "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
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{ "phy_polarity_detect", 25, 6, BIT(6) },
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{ "phy_open_detect", 25, 7, BIT(7) },
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{ "phy_short_detect", 25, 8, BIT(8) },
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{ "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
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{ "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
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};
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static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
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{
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int val;
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return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
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150, 30000, false);
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}
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static int phy_modify_check(struct phy_device *phydev, u8 reg,
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u16 mask, u16 set)
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{
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int ret;
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ret = phy_modify(phydev, reg, mask, set);
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if (ret)
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return ret;
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return tja11xx_check(phydev, reg, mask, set);
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}
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static int tja11xx_enable_reg_write(struct phy_device *phydev)
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{
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return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
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}
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static int tja11xx_enable_link_control(struct phy_device *phydev)
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{
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return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
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}
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static int tja11xx_disable_link_control(struct phy_device *phydev)
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{
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return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
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}
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static int tja11xx_wakeup(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MII_ECTRL);
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if (ret < 0)
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return ret;
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switch (ret & MII_ECTRL_POWER_MODE_MASK) {
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case MII_ECTRL_POWER_MODE_NO_CHANGE:
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break;
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case MII_ECTRL_POWER_MODE_NORMAL:
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ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
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if (ret)
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return ret;
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ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
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if (ret)
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return ret;
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break;
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case MII_ECTRL_POWER_MODE_STANDBY:
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ret = phy_modify_check(phydev, MII_ECTRL,
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MII_ECTRL_POWER_MODE_MASK,
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MII_ECTRL_POWER_MODE_STANDBY);
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if (ret)
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return ret;
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ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
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MII_ECTRL_POWER_MODE_NORMAL);
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if (ret)
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return ret;
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ret = phy_modify_check(phydev, MII_GENSTAT,
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MII_GENSTAT_PLL_LOCKED,
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MII_GENSTAT_PLL_LOCKED);
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if (ret)
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return ret;
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return tja11xx_enable_link_control(phydev);
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default:
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break;
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}
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return 0;
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}
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static int tja11xx_soft_reset(struct phy_device *phydev)
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{
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int ret;
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ret = tja11xx_enable_reg_write(phydev);
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if (ret)
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return ret;
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return genphy_soft_reset(phydev);
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}
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static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
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{
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bool finished = false;
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int ret;
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if (phydev->link)
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return 0;
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if (!phydev->drv->cable_test_start ||
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!phydev->drv->cable_test_get_status)
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return 0;
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ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
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if (ret)
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return ret;
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ret = phydev->drv->cable_test_start(phydev);
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if (ret)
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return ret;
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/* According to the documentation this test takes 100 usec */
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usleep_range(100, 200);
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ret = phydev->drv->cable_test_get_status(phydev, &finished);
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if (ret)
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return ret;
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if (finished)
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ethnl_cable_test_finished(phydev);
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return 0;
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}
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static int tja11xx_config_aneg(struct phy_device *phydev)
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{
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int ret, changed = 0;
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u16 ctl = 0;
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switch (phydev->master_slave_set) {
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case MASTER_SLAVE_CFG_MASTER_FORCE:
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ctl |= MII_CFG1_MASTER_SLAVE;
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break;
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case MASTER_SLAVE_CFG_SLAVE_FORCE:
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break;
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case MASTER_SLAVE_CFG_UNKNOWN:
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case MASTER_SLAVE_CFG_UNSUPPORTED:
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goto do_test;
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default:
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phydev_warn(phydev, "Unsupported Master/Slave mode\n");
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return -ENOTSUPP;
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}
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changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
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if (changed < 0)
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return changed;
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do_test:
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ret = tja11xx_config_aneg_cable_test(phydev);
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if (ret)
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return ret;
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return __genphy_config_aneg(phydev, changed);
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}
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static int tja11xx_config_init(struct phy_device *phydev)
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{
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int ret;
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ret = tja11xx_enable_reg_write(phydev);
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if (ret)
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return ret;
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phydev->autoneg = AUTONEG_DISABLE;
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phydev->speed = SPEED_100;
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phydev->duplex = DUPLEX_FULL;
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switch (phydev->phy_id & PHY_ID_MASK) {
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case PHY_ID_TJA1100:
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ret = phy_modify(phydev, MII_CFG1,
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MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
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MII_CFG1_LED_ENABLE,
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MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
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MII_CFG1_LED_ENABLE);
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if (ret)
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return ret;
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break;
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case PHY_ID_TJA1101:
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case PHY_ID_TJA1102:
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ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
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if (ret)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
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if (ret)
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return ret;
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ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
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MII_CFG2_SLEEP_REQUEST_TO_16MS);
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if (ret)
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return ret;
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ret = tja11xx_wakeup(phydev);
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if (ret < 0)
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return ret;
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/* ACK interrupts by reading the status register */
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ret = phy_read(phydev, MII_INTSRC);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int tja11xx_read_status(struct phy_device *phydev)
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{
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int ret;
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phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
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phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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ret = phy_read(phydev, MII_CFG1);
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if (ret < 0)
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return ret;
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if (ret & MII_CFG1_MASTER_SLAVE)
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phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
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else
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phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
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if (phydev->link) {
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ret = phy_read(phydev, MII_COMMSTAT);
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if (ret < 0)
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return ret;
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if (!(ret & MII_COMMSTAT_LINK_UP))
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phydev->link = 0;
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}
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return 0;
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}
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static int tja11xx_get_sqi(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MII_COMMSTAT);
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if (ret < 0)
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return ret;
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return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
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}
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static int tja11xx_get_sqi_max(struct phy_device *phydev)
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{
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return MII_COMMSTAT_SQI_MAX;
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}
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static int tja11xx_get_sset_count(struct phy_device *phydev)
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{
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return ARRAY_SIZE(tja11xx_hw_stats);
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}
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static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
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strncpy(data + i * ETH_GSTRING_LEN,
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tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
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}
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}
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static void tja11xx_get_stats(struct phy_device *phydev,
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struct ethtool_stats *stats, u64 *data)
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{
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int i, ret;
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for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
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ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
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if (ret < 0)
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data[i] = U64_MAX;
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else {
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data[i] = ret & tja11xx_hw_stats[i].mask;
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data[i] >>= tja11xx_hw_stats[i].off;
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}
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}
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}
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static int tja11xx_hwmon_read(struct device *dev,
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enum hwmon_sensor_types type,
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u32 attr, int channel, long *value)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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int ret;
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if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
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ret = phy_read(phydev, MII_INTSRC);
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if (ret < 0)
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return ret;
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*value = !!(ret & MII_INTSRC_TEMP_ERR);
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return 0;
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}
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if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
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ret = phy_read(phydev, MII_INTSRC);
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if (ret < 0)
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return ret;
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*value = !!(ret & MII_INTSRC_UV_ERR);
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return 0;
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}
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return -EOPNOTSUPP;
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}
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static umode_t tja11xx_hwmon_is_visible(const void *data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
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return 0444;
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if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
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return 0444;
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return 0;
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}
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static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
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HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
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HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
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NULL
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};
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static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
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.is_visible = tja11xx_hwmon_is_visible,
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.read = tja11xx_hwmon_read,
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};
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static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
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.ops = &tja11xx_hwmon_hwmon_ops,
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.info = tja11xx_hwmon_info,
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};
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static int tja11xx_hwmon_register(struct phy_device *phydev,
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struct tja11xx_priv *priv)
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{
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struct device *dev = &phydev->mdio.dev;
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int i;
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priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
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if (!priv->hwmon_name)
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return -ENOMEM;
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for (i = 0; priv->hwmon_name[i]; i++)
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if (hwmon_is_bad_char(priv->hwmon_name[i]))
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priv->hwmon_name[i] = '_';
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priv->hwmon_dev =
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devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
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phydev,
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&tja11xx_hwmon_chip_info,
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NULL);
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return PTR_ERR_OR_ZERO(priv->hwmon_dev);
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}
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static int tja11xx_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct tja11xx_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->phydev = phydev;
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return tja11xx_hwmon_register(phydev, priv);
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}
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static void tja1102_p1_register(struct work_struct *work)
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{
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struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
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phy_register_work);
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struct phy_device *phydev_phy0 = priv->phydev;
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struct mii_bus *bus = phydev_phy0->mdio.bus;
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struct device *dev = &phydev_phy0->mdio.dev;
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struct device_node *np = dev->of_node;
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struct device_node *child;
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int ret;
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for_each_available_child_of_node(np, child) {
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struct phy_device *phy;
|
|
int addr;
|
|
|
|
addr = of_mdio_parse_addr(dev, child);
|
|
if (addr < 0) {
|
|
dev_err(dev, "Can't parse addr\n");
|
|
continue;
|
|
} else if (addr != phydev_phy0->mdio.addr + 1) {
|
|
/* Currently we care only about double PHY chip TJA1102.
|
|
* If some day NXP will decide to bring chips with more
|
|
* PHYs, this logic should be reworked.
|
|
*/
|
|
dev_err(dev, "Unexpected address. Should be: %i\n",
|
|
phydev_phy0->mdio.addr + 1);
|
|
continue;
|
|
}
|
|
|
|
if (mdiobus_is_registered_device(bus, addr)) {
|
|
dev_err(dev, "device is already registered\n");
|
|
continue;
|
|
}
|
|
|
|
/* Real PHY ID of Port 1 is 0 */
|
|
phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
|
|
if (IS_ERR(phy)) {
|
|
dev_err(dev, "Can't create PHY device for Port 1: %i\n",
|
|
addr);
|
|
continue;
|
|
}
|
|
|
|
/* Overwrite parent device. phy_device_create() set parent to
|
|
* the mii_bus->dev, which is not correct in case.
|
|
*/
|
|
phy->mdio.dev.parent = dev;
|
|
|
|
ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
|
|
if (ret) {
|
|
/* All resources needed for Port 1 should be already
|
|
* available for Port 0. Both ports use the same
|
|
* interrupt line, so -EPROBE_DEFER would make no sense
|
|
* here.
|
|
*/
|
|
dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
|
|
ret);
|
|
phy_device_free(phy);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int tja1102_p0_probe(struct phy_device *phydev)
|
|
{
|
|
struct device *dev = &phydev->mdio.dev;
|
|
struct tja11xx_priv *priv;
|
|
int ret;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->phydev = phydev;
|
|
INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
|
|
|
|
ret = tja11xx_hwmon_register(phydev, priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
schedule_work(&priv->phy_register_work);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
|
|
{
|
|
int ret;
|
|
|
|
if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
|
|
return 0;
|
|
|
|
ret = phy_read(phydev, MII_PHYSID2);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* TJA1102 Port 1 has phyid 0 and doesn't support temperature
|
|
* and undervoltage alarms.
|
|
*/
|
|
if (port0)
|
|
return ret ? 1 : 0;
|
|
|
|
return !ret;
|
|
}
|
|
|
|
static int tja1102_p0_match_phy_device(struct phy_device *phydev)
|
|
{
|
|
return tja1102_match_phy_device(phydev, true);
|
|
}
|
|
|
|
static int tja1102_p1_match_phy_device(struct phy_device *phydev)
|
|
{
|
|
return tja1102_match_phy_device(phydev, false);
|
|
}
|
|
|
|
static int tja11xx_ack_interrupt(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
ret = phy_read(phydev, MII_INTSRC);
|
|
|
|
return (ret < 0) ? ret : 0;
|
|
}
|
|
|
|
static int tja11xx_config_intr(struct phy_device *phydev)
|
|
{
|
|
int value = 0;
|
|
int err;
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
|
|
err = tja11xx_ack_interrupt(phydev);
|
|
if (err)
|
|
return err;
|
|
|
|
value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP;
|
|
err = phy_write(phydev, MII_INTEN, value);
|
|
} else {
|
|
err = phy_write(phydev, MII_INTEN, value);
|
|
if (err)
|
|
return err;
|
|
|
|
err = tja11xx_ack_interrupt(phydev);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
|
|
{
|
|
int irq_status;
|
|
|
|
irq_status = phy_read(phydev, MII_INTSRC);
|
|
if (irq_status < 0) {
|
|
phy_error(phydev);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
if (!(irq_status & MII_INTSRC_MASK))
|
|
return IRQ_NONE;
|
|
|
|
phy_trigger_machine(phydev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int tja11xx_cable_test_start(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tja11xx_wakeup(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = tja11xx_disable_link_control(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
|
|
}
|
|
|
|
/*
|
|
* | BI_DA+ | BI_DA- | Result
|
|
* | open | open | open
|
|
* | + short to - | - short to + | short
|
|
* | short to Vdd | open | open
|
|
* | open | shot to Vdd | open
|
|
* | short to Vdd | short to Vdd | short
|
|
* | shot to GND | open | open
|
|
* | open | shot to GND | open
|
|
* | short to GND | shot to GND | short
|
|
* | connected to active link partner (master) | shot and open
|
|
*/
|
|
static int tja11xx_cable_test_report_trans(u32 result)
|
|
{
|
|
u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
|
|
|
|
if ((result & mask) == mask) {
|
|
/* connected to active link partner (master) */
|
|
return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
|
|
} else if ((result & mask) == 0) {
|
|
return ETHTOOL_A_CABLE_RESULT_CODE_OK;
|
|
} else if (result & MII_EXTSTAT_SHORT_DETECT) {
|
|
return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
|
|
} else if (result & MII_EXTSTAT_OPEN_DETECT) {
|
|
return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
|
|
} else {
|
|
return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
|
|
}
|
|
}
|
|
|
|
static int tja11xx_cable_test_report(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
ret = phy_read(phydev, MII_EXTSTAT);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
|
|
tja11xx_cable_test_report_trans(ret));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tja11xx_cable_test_get_status(struct phy_device *phydev,
|
|
bool *finished)
|
|
{
|
|
int ret;
|
|
|
|
*finished = false;
|
|
|
|
ret = phy_read(phydev, MII_ECTRL);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (!(ret & MII_ECTRL_CABLE_TEST)) {
|
|
*finished = true;
|
|
|
|
ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return tja11xx_cable_test_report(phydev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_driver tja11xx_driver[] = {
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
|
|
.name = "NXP TJA1100",
|
|
.features = PHY_BASIC_T1_FEATURES,
|
|
.probe = tja11xx_probe,
|
|
.soft_reset = tja11xx_soft_reset,
|
|
.config_aneg = tja11xx_config_aneg,
|
|
.config_init = tja11xx_config_init,
|
|
.read_status = tja11xx_read_status,
|
|
.get_sqi = tja11xx_get_sqi,
|
|
.get_sqi_max = tja11xx_get_sqi_max,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.set_loopback = genphy_loopback,
|
|
/* Statistics */
|
|
.get_sset_count = tja11xx_get_sset_count,
|
|
.get_strings = tja11xx_get_strings,
|
|
.get_stats = tja11xx_get_stats,
|
|
}, {
|
|
PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
|
|
.name = "NXP TJA1101",
|
|
.features = PHY_BASIC_T1_FEATURES,
|
|
.probe = tja11xx_probe,
|
|
.soft_reset = tja11xx_soft_reset,
|
|
.config_aneg = tja11xx_config_aneg,
|
|
.config_init = tja11xx_config_init,
|
|
.read_status = tja11xx_read_status,
|
|
.get_sqi = tja11xx_get_sqi,
|
|
.get_sqi_max = tja11xx_get_sqi_max,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.set_loopback = genphy_loopback,
|
|
/* Statistics */
|
|
.get_sset_count = tja11xx_get_sset_count,
|
|
.get_strings = tja11xx_get_strings,
|
|
.get_stats = tja11xx_get_stats,
|
|
}, {
|
|
.name = "NXP TJA1102 Port 0",
|
|
.features = PHY_BASIC_T1_FEATURES,
|
|
.flags = PHY_POLL_CABLE_TEST,
|
|
.probe = tja1102_p0_probe,
|
|
.soft_reset = tja11xx_soft_reset,
|
|
.config_aneg = tja11xx_config_aneg,
|
|
.config_init = tja11xx_config_init,
|
|
.read_status = tja11xx_read_status,
|
|
.get_sqi = tja11xx_get_sqi,
|
|
.get_sqi_max = tja11xx_get_sqi_max,
|
|
.match_phy_device = tja1102_p0_match_phy_device,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.set_loopback = genphy_loopback,
|
|
/* Statistics */
|
|
.get_sset_count = tja11xx_get_sset_count,
|
|
.get_strings = tja11xx_get_strings,
|
|
.get_stats = tja11xx_get_stats,
|
|
.config_intr = tja11xx_config_intr,
|
|
.handle_interrupt = tja11xx_handle_interrupt,
|
|
.cable_test_start = tja11xx_cable_test_start,
|
|
.cable_test_get_status = tja11xx_cable_test_get_status,
|
|
}, {
|
|
.name = "NXP TJA1102 Port 1",
|
|
.features = PHY_BASIC_T1_FEATURES,
|
|
.flags = PHY_POLL_CABLE_TEST,
|
|
/* currently no probe for Port 1 is need */
|
|
.soft_reset = tja11xx_soft_reset,
|
|
.config_aneg = tja11xx_config_aneg,
|
|
.config_init = tja11xx_config_init,
|
|
.read_status = tja11xx_read_status,
|
|
.get_sqi = tja11xx_get_sqi,
|
|
.get_sqi_max = tja11xx_get_sqi_max,
|
|
.match_phy_device = tja1102_p1_match_phy_device,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.set_loopback = genphy_loopback,
|
|
/* Statistics */
|
|
.get_sset_count = tja11xx_get_sset_count,
|
|
.get_strings = tja11xx_get_strings,
|
|
.get_stats = tja11xx_get_stats,
|
|
.config_intr = tja11xx_config_intr,
|
|
.handle_interrupt = tja11xx_handle_interrupt,
|
|
.cable_test_start = tja11xx_cable_test_start,
|
|
.cable_test_get_status = tja11xx_cable_test_get_status,
|
|
}
|
|
};
|
|
|
|
module_phy_driver(tja11xx_driver);
|
|
|
|
static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
|
|
|
|
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
|
|
MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
|
|
MODULE_LICENSE("GPL");
|