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ebf7cda0f9
Use runtime PM functionality interfaced with hwmod enable/idle functions, to replace direct clock operations and sysconfig handling. Due to reset sequence, pm_runtime_[get|put]_sync must be used, to avoid possible operations with the module under reset. Because of this and given that the driver uses spin_locks to protect their critical sections, we must use pm_runtime_irq_safe in order for the runtime ops to be happy, otherwise might_sleep_if checks in runtime framework will complain. The remaining pm_runtime out of iommu_enable and iommu_disable corresponds to paths that can be accessed through debugfs, some of them doesn't work if the module is not enabled first, but in future if the mmu is idled withouth freeing, these are needed to debug. Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org> Tested-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
334 lines
7.9 KiB
C
334 lines
7.9 KiB
C
/*
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* omap iommu: omap2/3 architecture specific functions
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
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* Paul Mundt and Toshihiro Kobayashi
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/omap-iommu.h>
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#include <linux/slab.h>
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#include <linux/stringify.h>
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#include <linux/platform_data/iommu-omap.h>
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#include "omap-iommu.h"
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/*
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* omap2 architecture specific register bit definitions
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*/
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#define IOMMU_ARCH_VERSION 0x00000011
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/* IRQSTATUS & IRQENABLE */
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#define MMU_IRQ_MULTIHITFAULT (1 << 4)
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#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
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#define MMU_IRQ_EMUMISS (1 << 2)
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#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
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#define MMU_IRQ_TLBMISS (1 << 0)
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#define __MMU_IRQ_FAULT \
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(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
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#define MMU_IRQ_MASK \
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(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
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#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
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#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
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/* MMU_CNTL */
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#define MMU_CNTL_SHIFT 1
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#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
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#define MMU_CNTL_EML_TLB (1 << 3)
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#define MMU_CNTL_TWL_EN (1 << 2)
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#define MMU_CNTL_MMU_EN (1 << 1)
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#define get_cam_va_mask(pgsz) \
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(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
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((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
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((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
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((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
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/* IOMMU errors */
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#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
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#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
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#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
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#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
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#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
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static void __iommu_set_twl(struct omap_iommu *obj, bool on)
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{
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u32 l = iommu_read_reg(obj, MMU_CNTL);
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if (on)
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iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
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else
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iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
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l &= ~MMU_CNTL_MASK;
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if (on)
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l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
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else
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l |= (MMU_CNTL_MMU_EN);
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iommu_write_reg(obj, l, MMU_CNTL);
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}
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static int omap2_iommu_enable(struct omap_iommu *obj)
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{
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u32 l, pa;
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if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
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return -EINVAL;
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pa = virt_to_phys(obj->iopgd);
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if (!IS_ALIGNED(pa, SZ_16K))
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return -EINVAL;
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l = iommu_read_reg(obj, MMU_REVISION);
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dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
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(l >> 4) & 0xf, l & 0xf);
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iommu_write_reg(obj, pa, MMU_TTB);
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__iommu_set_twl(obj, true);
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return 0;
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}
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static void omap2_iommu_disable(struct omap_iommu *obj)
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{
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u32 l = iommu_read_reg(obj, MMU_CNTL);
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l &= ~MMU_CNTL_MASK;
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iommu_write_reg(obj, l, MMU_CNTL);
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dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
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}
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static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
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{
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__iommu_set_twl(obj, false);
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}
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static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
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{
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u32 stat, da;
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u32 errs = 0;
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stat = iommu_read_reg(obj, MMU_IRQSTATUS);
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stat &= MMU_IRQ_MASK;
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if (!stat) {
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*ra = 0;
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return 0;
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}
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da = iommu_read_reg(obj, MMU_FAULT_AD);
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*ra = da;
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if (stat & MMU_IRQ_TLBMISS)
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errs |= OMAP_IOMMU_ERR_TLB_MISS;
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if (stat & MMU_IRQ_TRANSLATIONFAULT)
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errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
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if (stat & MMU_IRQ_EMUMISS)
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errs |= OMAP_IOMMU_ERR_EMU_MISS;
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if (stat & MMU_IRQ_TABLEWALKFAULT)
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errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
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if (stat & MMU_IRQ_MULTIHITFAULT)
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errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
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iommu_write_reg(obj, stat, MMU_IRQSTATUS);
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return errs;
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}
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static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
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{
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cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
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cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
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}
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static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
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{
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iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
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iommu_write_reg(obj, cr->ram, MMU_RAM);
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}
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static u32 omap2_cr_to_virt(struct cr_regs *cr)
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{
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u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
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u32 mask = get_cam_va_mask(cr->cam & page_size);
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return cr->cam & mask;
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}
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static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
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struct iotlb_entry *e)
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{
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struct cr_regs *cr;
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if (e->da & ~(get_cam_va_mask(e->pgsz))) {
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dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
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e->da);
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return ERR_PTR(-EINVAL);
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}
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cr = kmalloc(sizeof(*cr), GFP_KERNEL);
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if (!cr)
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return ERR_PTR(-ENOMEM);
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cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
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cr->ram = e->pa | e->endian | e->elsz | e->mixed;
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return cr;
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}
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static inline int omap2_cr_valid(struct cr_regs *cr)
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{
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return cr->cam & MMU_CAM_V;
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}
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static u32 omap2_get_pte_attr(struct iotlb_entry *e)
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{
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u32 attr;
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attr = e->mixed << 5;
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attr |= e->endian;
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attr |= e->elsz >> 3;
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attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
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(e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
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return attr;
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}
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static ssize_t
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omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
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{
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char *p = buf;
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/* FIXME: Need more detail analysis of cam/ram */
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p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
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(cr->cam & MMU_CAM_P) ? 1 : 0);
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return p - buf;
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}
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#define pr_reg(name) \
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do { \
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ssize_t bytes; \
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const char *str = "%20s: %08x\n"; \
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const int maxcol = 32; \
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bytes = snprintf(p, maxcol, str, __stringify(name), \
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iommu_read_reg(obj, MMU_##name)); \
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p += bytes; \
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len -= bytes; \
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if (len < maxcol) \
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goto out; \
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} while (0)
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static ssize_t
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omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
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{
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char *p = buf;
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pr_reg(REVISION);
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pr_reg(IRQSTATUS);
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pr_reg(IRQENABLE);
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pr_reg(WALKING_ST);
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pr_reg(CNTL);
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pr_reg(FAULT_AD);
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pr_reg(TTB);
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pr_reg(LOCK);
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pr_reg(LD_TLB);
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pr_reg(CAM);
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pr_reg(RAM);
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pr_reg(GFLUSH);
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pr_reg(FLUSH_ENTRY);
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pr_reg(READ_CAM);
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pr_reg(READ_RAM);
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pr_reg(EMU_FAULT_AD);
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out:
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return p - buf;
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}
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static void omap2_iommu_save_ctx(struct omap_iommu *obj)
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{
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int i;
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u32 *p = obj->ctx;
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for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
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p[i] = iommu_read_reg(obj, i * sizeof(u32));
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dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
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}
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BUG_ON(p[0] != IOMMU_ARCH_VERSION);
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}
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static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
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{
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int i;
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u32 *p = obj->ctx;
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for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
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iommu_write_reg(obj, p[i], i * sizeof(u32));
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dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
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}
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BUG_ON(p[0] != IOMMU_ARCH_VERSION);
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}
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static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
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{
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e->da = cr->cam & MMU_CAM_VATAG_MASK;
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e->pa = cr->ram & MMU_RAM_PADDR_MASK;
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e->valid = cr->cam & MMU_CAM_V;
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e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
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e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
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e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
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e->mixed = cr->ram & MMU_RAM_MIXED;
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}
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static const struct iommu_functions omap2_iommu_ops = {
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.version = IOMMU_ARCH_VERSION,
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.enable = omap2_iommu_enable,
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.disable = omap2_iommu_disable,
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.set_twl = omap2_iommu_set_twl,
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.fault_isr = omap2_iommu_fault_isr,
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.tlb_read_cr = omap2_tlb_read_cr,
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.tlb_load_cr = omap2_tlb_load_cr,
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.cr_to_e = omap2_cr_to_e,
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.cr_to_virt = omap2_cr_to_virt,
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.alloc_cr = omap2_alloc_cr,
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.cr_valid = omap2_cr_valid,
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.dump_cr = omap2_dump_cr,
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.get_pte_attr = omap2_get_pte_attr,
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.save_ctx = omap2_iommu_save_ctx,
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.restore_ctx = omap2_iommu_restore_ctx,
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.dump_ctx = omap2_iommu_dump_ctx,
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};
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static int __init omap2_iommu_init(void)
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{
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return omap_install_iommu_arch(&omap2_iommu_ops);
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}
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module_init(omap2_iommu_init);
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static void __exit omap2_iommu_exit(void)
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{
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omap_uninstall_iommu_arch(&omap2_iommu_ops);
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}
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module_exit(omap2_iommu_exit);
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MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
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MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
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MODULE_LICENSE("GPL v2");
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