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![Conor Dooley](/assets/img/avatar_default.png)
This reverts commit232ccac1bd
. On the subject of suspend, the RISC-V SBI spec states: This does not cover whether any given events actually reach the hart or not, just what the hart will do if it receives an event. On PolarFire SoC, and potentially other SiFive based implementations, events from the RISC-V timer do reach a hart during suspend. This is not the case for the implementation on the Allwinner D1 - there timer events are not received during suspend. To fix this, the CLOCK_EVT_FEAT_C3STOP (mis)feature was enabled for the timer driver - but this has broken both RCU stall detection and timers generally on PolarFire SoC and potentially other SiFive based implementations. If an AXI read to the PCIe controller on PolarFire SoC times out, the system will stall, however, with CLOCK_EVT_FEAT_C3STOP active, the system just locks up without RCU stalling: io scheduler mq-deadline registered io scheduler kyber registered microchip-pcie 2000000000.pcie: host bridge /soc/pcie@2000000000 ranges: microchip-pcie 2000000000.pcie: MEM 0x2008000000..0x2087ffffff -> 0x0008000000 microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer microchip-pcie 2000000000.pcie: axi read request error microchip-pcie 2000000000.pcie: axi read timeout microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer Freeing initrd memory: 7332K Similarly issues were reported with clock_nanosleep() - with a test app that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=250 & the blamed commit in place, the sleep times are rounded up to the next jiffy: == CPU: 1 == == CPU: 2 == == CPU: 3 == == CPU: 4 == Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179 Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193 Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000 Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000 Samples: 521 Samples: 521 Samples: 521 Samples: 521 Fortunately, the D1 has a second timer, which is "currently used in preference to the RISC-V/SBI timer driver" so a revert here does not hurt operation of D1 in its current form. Ultimately, a DeviceTree property (or node) will be added to encode the behaviour of the timers, but until then revert the addition of CLOCK_EVT_FEAT_C3STOP. Fixes:232ccac1bd
("clocksource/drivers/riscv: Events are stopped during CPU suspend") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/ Link: https://github.com/riscv-non-isa/riscv-sbi-doc/issues/98/ Link: https://lore.kernel.org/linux-riscv/bf6d3b1f-f703-4a25-833e-972a44a04114@sholland.org/ Link: https://lore.kernel.org/r/20221122121620.3522431-1-conor.dooley@microchip.com
195 lines
5.1 KiB
C
195 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* All RISC-V systems have a timer attached to every hart. These timers can
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* either be read from the "time" and "timeh" CSRs, and can use the SBI to
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* setup events, or directly accessed using MMIO registers.
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*/
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#define pr_fmt(fmt) "riscv-timer: " fmt
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/sched_clock.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <clocksource/timer-riscv.h>
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#include <asm/smp.h>
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#include <asm/hwcap.h>
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#include <asm/sbi.h>
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#include <asm/timex.h>
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static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
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static int riscv_clock_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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u64 next_tval = get_cycles64() + delta;
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csr_set(CSR_IE, IE_TIE);
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if (static_branch_likely(&riscv_sstc_available)) {
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#if defined(CONFIG_32BIT)
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csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
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csr_write(CSR_STIMECMPH, next_tval >> 32);
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#else
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csr_write(CSR_STIMECMP, next_tval);
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#endif
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} else
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sbi_set_timer(next_tval);
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return 0;
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}
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static unsigned int riscv_clock_event_irq;
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static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
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.name = "riscv_timer_clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 100,
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.set_next_event = riscv_clock_next_event,
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};
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/*
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* It is guaranteed that all the timers across all the harts are synchronized
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* within one tick of each other, so while this could technically go
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* backwards when hopping between CPUs, practically it won't happen.
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*/
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static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
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{
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return get_cycles64();
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}
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static u64 notrace riscv_sched_clock(void)
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{
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return get_cycles64();
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}
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static struct clocksource riscv_clocksource = {
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.name = "riscv_clocksource",
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.rating = 300,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = riscv_clocksource_rdtime,
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};
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static int riscv_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
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ce->cpumask = cpumask_of(cpu);
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ce->irq = riscv_clock_event_irq;
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clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
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enable_percpu_irq(riscv_clock_event_irq,
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irq_get_trigger_type(riscv_clock_event_irq));
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return 0;
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}
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static int riscv_timer_dying_cpu(unsigned int cpu)
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{
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disable_percpu_irq(riscv_clock_event_irq);
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return 0;
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}
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void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
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{
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*mult = riscv_clocksource.mult;
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*shift = riscv_clocksource.shift;
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}
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EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
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/* called directly from the low-level interrupt handler */
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static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
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csr_clear(CSR_IE, IE_TIE);
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evdev->event_handler(evdev);
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return IRQ_HANDLED;
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}
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static int __init riscv_timer_init_dt(struct device_node *n)
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{
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int cpuid, error;
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unsigned long hartid;
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struct device_node *child;
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struct irq_domain *domain;
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error = riscv_of_processor_hartid(n, &hartid);
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if (error < 0) {
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pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
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n, hartid);
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return error;
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}
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cpuid = riscv_hartid_to_cpuid(hartid);
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if (cpuid < 0) {
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pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
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return cpuid;
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}
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if (cpuid != smp_processor_id())
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return 0;
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domain = NULL;
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child = of_get_compatible_child(n, "riscv,cpu-intc");
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if (!child) {
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pr_err("Failed to find INTC node [%pOF]\n", n);
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return -ENODEV;
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}
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domain = irq_find_host(child);
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of_node_put(child);
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if (!domain) {
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pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
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return -ENODEV;
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}
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riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
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if (!riscv_clock_event_irq) {
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pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
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return -ENODEV;
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}
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pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
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__func__, cpuid, hartid);
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error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
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if (error) {
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pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
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error, cpuid);
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return error;
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}
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sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
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error = request_percpu_irq(riscv_clock_event_irq,
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riscv_timer_interrupt,
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"riscv-timer", &riscv_clock_event);
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if (error) {
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pr_err("registering percpu irq failed [%d]\n", error);
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return error;
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}
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error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
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"clockevents/riscv/timer:starting",
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riscv_timer_starting_cpu, riscv_timer_dying_cpu);
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if (error)
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pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
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error);
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if (riscv_isa_extension_available(NULL, SSTC)) {
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pr_info("Timer interrupt in S-mode is available via sstc extension\n");
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static_branch_enable(&riscv_sstc_available);
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}
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return error;
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}
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TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
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