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![Perry Yuan](/assets/img/avatar_default.png)
When the amd_pstate driver is built-in users still need a method to be able enable or disable it depending upon their circumstance. Add support for an early parameter to do this. There is some performance degradation on a number of ASICs in the passive mode. This performance issue was originally discovered in shared memory systems but it has been proven that certain workloads on MSR systems also suffer performance issues. Set the amd-pstate driver as disabled by default to temporarily mitigate the performance problem. 1) with `amd_pstate=disable`, pstate driver will be disabled to load at kernel booting. 2) with `amd_pstate=passive`, pstate driver will be enabled and loaded as non-autonomous working mode supported in the low-level power management firmware. 3) If neither parameter is specified, the driver will be disabled by default to avoid triggering performance regressions in certain ASICs Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Tested-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
688 lines
18 KiB
C
688 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* amd-pstate.c - AMD Processor P-state Frequency Driver
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*
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* Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Author: Huang Rui <ray.huang@amd.com>
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*
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* AMD P-State introduces a new CPU performance scaling design for AMD
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* processors using the ACPI Collaborative Performance and Power Control (CPPC)
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* feature which works with the AMD SMU firmware providing a finer grained
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* frequency control range. It is to replace the legacy ACPI P-States control,
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* allows a flexible, low-latency interface for the Linux kernel to directly
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* communicate the performance hints to hardware.
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*
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* AMD P-State is supported on recent AMD Zen base CPU series include some of
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* Zen2 and Zen3 processors. _CPC needs to be present in the ACPI tables of AMD
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* P-State supported system. And there are two types of hardware implementations
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* for AMD P-State: 1) Full MSR Solution and 2) Shared Memory Solution.
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* X86_FEATURE_CPPC CPU feature flag is used to distinguish the different types.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/sched.h>
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#include <linux/cpufreq.h>
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#include <linux/compiler.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/uaccess.h>
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#include <linux/static_call.h>
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#include <linux/amd-pstate.h>
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#include <acpi/processor.h>
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#include <acpi/cppc_acpi.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#include <asm/cpu_device_id.h>
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#include "amd-pstate-trace.h"
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#define AMD_PSTATE_TRANSITION_LATENCY 20000
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#define AMD_PSTATE_TRANSITION_DELAY 1000
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/*
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* TODO: We need more time to fine tune processors with shared memory solution
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* with community together.
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*
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* There are some performance drops on the CPU benchmarks which reports from
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* Suse. We are co-working with them to fine tune the shared memory solution. So
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* we disable it by default to go acpi-cpufreq on these processors and add a
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* module parameter to be able to enable it manually for debugging.
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*/
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static struct cpufreq_driver amd_pstate_driver;
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static int cppc_load __initdata;
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static inline int pstate_enable(bool enable)
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{
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return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable);
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}
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static int cppc_enable(bool enable)
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{
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int cpu, ret = 0;
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for_each_present_cpu(cpu) {
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ret = cppc_set_enable(cpu, enable);
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if (ret)
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return ret;
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}
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return ret;
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}
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DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
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static inline int amd_pstate_enable(bool enable)
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{
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return static_call(amd_pstate_enable)(enable);
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}
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static int pstate_init_perf(struct amd_cpudata *cpudata)
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{
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u64 cap1;
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u32 highest_perf;
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int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
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&cap1);
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if (ret)
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return ret;
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/*
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* TODO: Introduce AMD specific power feature.
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*
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* CPPC entry doesn't indicate the highest performance in some ASICs.
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*/
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highest_perf = amd_get_highest_perf();
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if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
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highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
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WRITE_ONCE(cpudata->highest_perf, highest_perf);
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WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
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WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
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WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
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return 0;
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}
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static int cppc_init_perf(struct amd_cpudata *cpudata)
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{
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struct cppc_perf_caps cppc_perf;
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u32 highest_perf;
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
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if (ret)
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return ret;
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highest_perf = amd_get_highest_perf();
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if (highest_perf > cppc_perf.highest_perf)
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highest_perf = cppc_perf.highest_perf;
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WRITE_ONCE(cpudata->highest_perf, highest_perf);
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WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
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WRITE_ONCE(cpudata->lowest_nonlinear_perf,
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cppc_perf.lowest_nonlinear_perf);
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WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
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return 0;
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}
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DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf);
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static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
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{
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return static_call(amd_pstate_init_perf)(cpudata);
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}
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static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
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u32 des_perf, u32 max_perf, bool fast_switch)
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{
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if (fast_switch)
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wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));
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else
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wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
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READ_ONCE(cpudata->cppc_req_cached));
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}
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static void cppc_update_perf(struct amd_cpudata *cpudata,
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u32 min_perf, u32 des_perf,
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u32 max_perf, bool fast_switch)
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{
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struct cppc_perf_ctrls perf_ctrls;
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perf_ctrls.max_perf = max_perf;
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perf_ctrls.min_perf = min_perf;
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perf_ctrls.desired_perf = des_perf;
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cppc_set_perf(cpudata->cpu, &perf_ctrls);
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}
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DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
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static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
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u32 min_perf, u32 des_perf,
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u32 max_perf, bool fast_switch)
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{
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static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,
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max_perf, fast_switch);
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}
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static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
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{
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u64 aperf, mperf, tsc;
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unsigned long flags;
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local_irq_save(flags);
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rdmsrl(MSR_IA32_APERF, aperf);
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rdmsrl(MSR_IA32_MPERF, mperf);
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tsc = rdtsc();
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if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) {
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local_irq_restore(flags);
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return false;
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}
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local_irq_restore(flags);
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cpudata->cur.aperf = aperf;
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cpudata->cur.mperf = mperf;
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cpudata->cur.tsc = tsc;
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cpudata->cur.aperf -= cpudata->prev.aperf;
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cpudata->cur.mperf -= cpudata->prev.mperf;
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cpudata->cur.tsc -= cpudata->prev.tsc;
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cpudata->prev.aperf = aperf;
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cpudata->prev.mperf = mperf;
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cpudata->prev.tsc = tsc;
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cpudata->freq = div64_u64((cpudata->cur.aperf * cpu_khz), cpudata->cur.mperf);
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return true;
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}
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static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
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u32 des_perf, u32 max_perf, bool fast_switch)
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{
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u64 prev = READ_ONCE(cpudata->cppc_req_cached);
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u64 value = prev;
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des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
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value &= ~AMD_CPPC_MIN_PERF(~0L);
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value |= AMD_CPPC_MIN_PERF(min_perf);
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value &= ~AMD_CPPC_DES_PERF(~0L);
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value |= AMD_CPPC_DES_PERF(des_perf);
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value &= ~AMD_CPPC_MAX_PERF(~0L);
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value |= AMD_CPPC_MAX_PERF(max_perf);
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if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) {
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trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq,
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cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc,
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cpudata->cpu, (value != prev), fast_switch);
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}
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if (value == prev)
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return;
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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amd_pstate_update_perf(cpudata, min_perf, des_perf,
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max_perf, fast_switch);
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}
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static int amd_pstate_verify(struct cpufreq_policy_data *policy)
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{
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cpufreq_verify_within_cpu_limits(policy);
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return 0;
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}
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static int amd_pstate_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct cpufreq_freqs freqs;
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struct amd_cpudata *cpudata = policy->driver_data;
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unsigned long max_perf, min_perf, des_perf, cap_perf;
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if (!cpudata->max_freq)
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return -ENODEV;
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cap_perf = READ_ONCE(cpudata->highest_perf);
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min_perf = READ_ONCE(cpudata->lowest_perf);
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max_perf = cap_perf;
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freqs.old = policy->cur;
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freqs.new = target_freq;
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des_perf = DIV_ROUND_CLOSEST(target_freq * cap_perf,
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cpudata->max_freq);
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cpufreq_freq_transition_begin(policy, &freqs);
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amd_pstate_update(cpudata, min_perf, des_perf,
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max_perf, false);
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cpufreq_freq_transition_end(policy, &freqs, false);
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return 0;
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}
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static void amd_pstate_adjust_perf(unsigned int cpu,
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unsigned long _min_perf,
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unsigned long target_perf,
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unsigned long capacity)
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{
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unsigned long max_perf, min_perf, des_perf,
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cap_perf, lowest_nonlinear_perf;
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struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
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struct amd_cpudata *cpudata = policy->driver_data;
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cap_perf = READ_ONCE(cpudata->highest_perf);
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lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
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des_perf = cap_perf;
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if (target_perf < capacity)
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des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity);
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min_perf = READ_ONCE(cpudata->highest_perf);
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if (_min_perf < capacity)
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min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity);
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if (min_perf < lowest_nonlinear_perf)
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min_perf = lowest_nonlinear_perf;
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max_perf = cap_perf;
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if (max_perf < min_perf)
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max_perf = min_perf;
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amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true);
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}
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static int amd_get_min_freq(struct amd_cpudata *cpudata)
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{
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struct cppc_perf_caps cppc_perf;
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
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if (ret)
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return ret;
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/* Switch to khz */
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return cppc_perf.lowest_freq * 1000;
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}
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static int amd_get_max_freq(struct amd_cpudata *cpudata)
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{
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struct cppc_perf_caps cppc_perf;
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u32 max_perf, max_freq, nominal_freq, nominal_perf;
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u64 boost_ratio;
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
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if (ret)
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return ret;
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nominal_freq = cppc_perf.nominal_freq;
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nominal_perf = READ_ONCE(cpudata->nominal_perf);
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max_perf = READ_ONCE(cpudata->highest_perf);
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boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT,
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nominal_perf);
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max_freq = nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT;
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/* Switch to khz */
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return max_freq * 1000;
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}
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static int amd_get_nominal_freq(struct amd_cpudata *cpudata)
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{
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struct cppc_perf_caps cppc_perf;
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
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if (ret)
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return ret;
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/* Switch to khz */
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return cppc_perf.nominal_freq * 1000;
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}
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static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata)
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{
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struct cppc_perf_caps cppc_perf;
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u32 lowest_nonlinear_freq, lowest_nonlinear_perf,
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nominal_freq, nominal_perf;
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u64 lowest_nonlinear_ratio;
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
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if (ret)
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return ret;
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nominal_freq = cppc_perf.nominal_freq;
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nominal_perf = READ_ONCE(cpudata->nominal_perf);
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lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf;
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lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT,
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nominal_perf);
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lowest_nonlinear_freq = nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT;
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/* Switch to khz */
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return lowest_nonlinear_freq * 1000;
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}
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static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state)
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{
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struct amd_cpudata *cpudata = policy->driver_data;
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int ret;
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if (!cpudata->boost_supported) {
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pr_err("Boost mode is not supported by this processor or SBIOS\n");
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return -EINVAL;
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}
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if (state)
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policy->cpuinfo.max_freq = cpudata->max_freq;
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else
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policy->cpuinfo.max_freq = cpudata->nominal_freq;
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policy->max = policy->cpuinfo.max_freq;
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ret = freq_qos_update_request(&cpudata->req[1],
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policy->cpuinfo.max_freq);
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if (ret < 0)
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return ret;
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return 0;
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}
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static void amd_pstate_boost_init(struct amd_cpudata *cpudata)
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{
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u32 highest_perf, nominal_perf;
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highest_perf = READ_ONCE(cpudata->highest_perf);
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nominal_perf = READ_ONCE(cpudata->nominal_perf);
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if (highest_perf <= nominal_perf)
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return;
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cpudata->boost_supported = true;
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amd_pstate_driver.boost_enabled = true;
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}
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static void amd_perf_ctl_reset(unsigned int cpu)
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{
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wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
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}
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static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
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{
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int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
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struct device *dev;
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struct amd_cpudata *cpudata;
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/*
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* Resetting PERF_CTL_MSR will put the CPU in P0 frequency,
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* which is ideal for initialization process.
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*/
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amd_perf_ctl_reset(policy->cpu);
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dev = get_cpu_device(policy->cpu);
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if (!dev)
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return -ENODEV;
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cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
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if (!cpudata)
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return -ENOMEM;
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cpudata->cpu = policy->cpu;
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ret = amd_pstate_init_perf(cpudata);
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if (ret)
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goto free_cpudata1;
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min_freq = amd_get_min_freq(cpudata);
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max_freq = amd_get_max_freq(cpudata);
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nominal_freq = amd_get_nominal_freq(cpudata);
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lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata);
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if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) {
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dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n",
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min_freq, max_freq);
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ret = -EINVAL;
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goto free_cpudata1;
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}
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policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY;
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policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY;
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policy->min = min_freq;
|
|
policy->max = max_freq;
|
|
|
|
policy->cpuinfo.min_freq = min_freq;
|
|
policy->cpuinfo.max_freq = max_freq;
|
|
|
|
/* It will be updated by governor */
|
|
policy->cur = policy->cpuinfo.min_freq;
|
|
|
|
if (boot_cpu_has(X86_FEATURE_CPPC))
|
|
policy->fast_switch_possible = true;
|
|
|
|
ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0],
|
|
FREQ_QOS_MIN, policy->cpuinfo.min_freq);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
|
|
goto free_cpudata1;
|
|
}
|
|
|
|
ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1],
|
|
FREQ_QOS_MAX, policy->cpuinfo.max_freq);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
|
|
goto free_cpudata2;
|
|
}
|
|
|
|
/* Initial processor data capability frequencies */
|
|
cpudata->max_freq = max_freq;
|
|
cpudata->min_freq = min_freq;
|
|
cpudata->nominal_freq = nominal_freq;
|
|
cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq;
|
|
|
|
policy->driver_data = cpudata;
|
|
|
|
amd_pstate_boost_init(cpudata);
|
|
|
|
return 0;
|
|
|
|
free_cpudata2:
|
|
freq_qos_remove_request(&cpudata->req[0]);
|
|
free_cpudata1:
|
|
kfree(cpudata);
|
|
return ret;
|
|
}
|
|
|
|
static int amd_pstate_cpu_exit(struct cpufreq_policy *policy)
|
|
{
|
|
struct amd_cpudata *cpudata = policy->driver_data;
|
|
|
|
freq_qos_remove_request(&cpudata->req[1]);
|
|
freq_qos_remove_request(&cpudata->req[0]);
|
|
kfree(cpudata);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
|
|
{
|
|
int ret;
|
|
|
|
ret = amd_pstate_enable(true);
|
|
if (ret)
|
|
pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
|
|
{
|
|
int ret;
|
|
|
|
ret = amd_pstate_enable(false);
|
|
if (ret)
|
|
pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Sysfs attributes */
|
|
|
|
/*
|
|
* This frequency is to indicate the maximum hardware frequency.
|
|
* If boost is not active but supported, the frequency will be larger than the
|
|
* one in cpuinfo.
|
|
*/
|
|
static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy,
|
|
char *buf)
|
|
{
|
|
int max_freq;
|
|
struct amd_cpudata *cpudata = policy->driver_data;
|
|
|
|
max_freq = amd_get_max_freq(cpudata);
|
|
if (max_freq < 0)
|
|
return max_freq;
|
|
|
|
return sprintf(&buf[0], "%u\n", max_freq);
|
|
}
|
|
|
|
static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy,
|
|
char *buf)
|
|
{
|
|
int freq;
|
|
struct amd_cpudata *cpudata = policy->driver_data;
|
|
|
|
freq = amd_get_lowest_nonlinear_freq(cpudata);
|
|
if (freq < 0)
|
|
return freq;
|
|
|
|
return sprintf(&buf[0], "%u\n", freq);
|
|
}
|
|
|
|
/*
|
|
* In some of ASICs, the highest_perf is not the one in the _CPC table, so we
|
|
* need to expose it to sysfs.
|
|
*/
|
|
static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
|
|
char *buf)
|
|
{
|
|
u32 perf;
|
|
struct amd_cpudata *cpudata = policy->driver_data;
|
|
|
|
perf = READ_ONCE(cpudata->highest_perf);
|
|
|
|
return sprintf(&buf[0], "%u\n", perf);
|
|
}
|
|
|
|
cpufreq_freq_attr_ro(amd_pstate_max_freq);
|
|
cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
|
|
|
|
cpufreq_freq_attr_ro(amd_pstate_highest_perf);
|
|
|
|
static struct freq_attr *amd_pstate_attr[] = {
|
|
&amd_pstate_max_freq,
|
|
&amd_pstate_lowest_nonlinear_freq,
|
|
&amd_pstate_highest_perf,
|
|
NULL,
|
|
};
|
|
|
|
static struct cpufreq_driver amd_pstate_driver = {
|
|
.flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
|
|
.verify = amd_pstate_verify,
|
|
.target = amd_pstate_target,
|
|
.init = amd_pstate_cpu_init,
|
|
.exit = amd_pstate_cpu_exit,
|
|
.suspend = amd_pstate_cpu_suspend,
|
|
.resume = amd_pstate_cpu_resume,
|
|
.set_boost = amd_pstate_set_boost,
|
|
.name = "amd-pstate",
|
|
.attr = amd_pstate_attr,
|
|
};
|
|
|
|
static int __init amd_pstate_init(void)
|
|
{
|
|
int ret;
|
|
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
|
|
return -ENODEV;
|
|
/*
|
|
* by default the pstate driver is disabled to load
|
|
* enable the amd_pstate passive mode driver explicitly
|
|
* with amd_pstate=passive in kernel command line
|
|
*/
|
|
if (!cppc_load) {
|
|
pr_debug("driver load is disabled, boot with amd_pstate=passive to enable this\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!acpi_cpc_valid()) {
|
|
pr_warn_once("the _CPC object is not present in SBIOS or ACPI disabled\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* don't keep reloading if cpufreq_driver exists */
|
|
if (cpufreq_get_current_driver())
|
|
return -EEXIST;
|
|
|
|
/* capability check */
|
|
if (boot_cpu_has(X86_FEATURE_CPPC)) {
|
|
pr_debug("AMD CPPC MSR based functionality is supported\n");
|
|
amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
|
|
} else {
|
|
pr_debug("AMD CPPC shared memory based functionality is supported\n");
|
|
static_call_update(amd_pstate_enable, cppc_enable);
|
|
static_call_update(amd_pstate_init_perf, cppc_init_perf);
|
|
static_call_update(amd_pstate_update_perf, cppc_update_perf);
|
|
}
|
|
|
|
/* enable amd pstate feature */
|
|
ret = amd_pstate_enable(true);
|
|
if (ret) {
|
|
pr_err("failed to enable amd-pstate with return %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = cpufreq_register_driver(&amd_pstate_driver);
|
|
if (ret)
|
|
pr_err("failed to register amd_pstate_driver with return %d\n",
|
|
ret);
|
|
|
|
return ret;
|
|
}
|
|
device_initcall(amd_pstate_init);
|
|
|
|
static int __init amd_pstate_param(char *str)
|
|
{
|
|
if (!str)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(str, "disable")) {
|
|
cppc_load = 0;
|
|
pr_info("driver is explicitly disabled\n");
|
|
} else if (!strcmp(str, "passive"))
|
|
cppc_load = 1;
|
|
|
|
return 0;
|
|
}
|
|
early_param("amd_pstate", amd_pstate_param);
|
|
|
|
MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
|
|
MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
|
|
MODULE_LICENSE("GPL");
|