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![Yang Yingliang](/assets/img/avatar_default.png)
If regulator_get_voltage() fails, it should return the error code in
mtk_cpu_dvfs_info_init().
Fixes: 0daa47325b
("cpufreq: mediatek: Link CCI device to CPU")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
784 lines
20 KiB
C
784 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 Linaro Ltd.
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* Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpumask.h>
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#include <linux/minmax.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/regulator/consumer.h>
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struct mtk_cpufreq_platform_data {
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int min_volt_shift;
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int max_volt_shift;
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int proc_max_volt;
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int sram_min_volt;
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int sram_max_volt;
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bool ccifreq_supported;
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};
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/*
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* The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
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* on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
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* Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
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* voltage inputs need to be controlled under a hardware limitation:
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* 100mV < Vsram - Vproc < 200mV
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*
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* When scaling the clock frequency of a CPU clock domain, the clock source
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* needs to be switched to another stable PLL clock temporarily until
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* the original PLL becomes stable at target frequency.
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*/
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struct mtk_cpu_dvfs_info {
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struct cpumask cpus;
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struct device *cpu_dev;
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struct device *cci_dev;
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struct regulator *proc_reg;
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struct regulator *sram_reg;
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struct clk *cpu_clk;
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struct clk *inter_clk;
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struct list_head list_head;
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int intermediate_voltage;
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bool need_voltage_tracking;
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int vproc_on_boot;
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int pre_vproc;
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/* Avoid race condition for regulators between notify and policy */
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struct mutex reg_lock;
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struct notifier_block opp_nb;
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unsigned int opp_cpu;
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unsigned long current_freq;
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const struct mtk_cpufreq_platform_data *soc_data;
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int vtrack_max;
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bool ccifreq_bound;
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};
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static struct platform_device *cpufreq_pdev;
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static LIST_HEAD(dvfs_info_list);
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static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
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{
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struct mtk_cpu_dvfs_info *info;
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list_for_each_entry(info, &dvfs_info_list, list_head) {
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if (cpumask_test_cpu(cpu, &info->cpus))
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return info;
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}
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return NULL;
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}
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static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
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int new_vproc)
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{
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const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
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struct regulator *proc_reg = info->proc_reg;
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struct regulator *sram_reg = info->sram_reg;
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int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
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int retry = info->vtrack_max;
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pre_vproc = regulator_get_voltage(proc_reg);
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if (pre_vproc < 0) {
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dev_err(info->cpu_dev,
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"invalid Vproc value: %d\n", pre_vproc);
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return pre_vproc;
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}
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pre_vsram = regulator_get_voltage(sram_reg);
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if (pre_vsram < 0) {
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dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
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return pre_vsram;
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}
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new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
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soc_data->sram_min_volt, soc_data->sram_max_volt);
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do {
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if (pre_vproc <= new_vproc) {
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vsram = clamp(pre_vproc + soc_data->max_volt_shift,
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soc_data->sram_min_volt, new_vsram);
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ret = regulator_set_voltage(sram_reg, vsram,
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soc_data->sram_max_volt);
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if (ret)
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return ret;
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if (vsram == soc_data->sram_max_volt ||
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new_vsram == soc_data->sram_min_volt)
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vproc = new_vproc;
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else
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vproc = vsram - soc_data->min_volt_shift;
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ret = regulator_set_voltage(proc_reg, vproc,
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soc_data->proc_max_volt);
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if (ret) {
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regulator_set_voltage(sram_reg, pre_vsram,
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soc_data->sram_max_volt);
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return ret;
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}
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} else if (pre_vproc > new_vproc) {
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vproc = max(new_vproc,
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pre_vsram - soc_data->max_volt_shift);
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ret = regulator_set_voltage(proc_reg, vproc,
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soc_data->proc_max_volt);
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if (ret)
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return ret;
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if (vproc == new_vproc)
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vsram = new_vsram;
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else
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vsram = max(new_vsram,
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vproc + soc_data->min_volt_shift);
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ret = regulator_set_voltage(sram_reg, vsram,
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soc_data->sram_max_volt);
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if (ret) {
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regulator_set_voltage(proc_reg, pre_vproc,
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soc_data->proc_max_volt);
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return ret;
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}
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}
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pre_vproc = vproc;
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pre_vsram = vsram;
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if (--retry < 0) {
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dev_err(info->cpu_dev,
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"over loop count, failed to set voltage\n");
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return -EINVAL;
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}
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} while (vproc != new_vproc || vsram != new_vsram);
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return 0;
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}
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static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
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{
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const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
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int ret;
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if (info->need_voltage_tracking)
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ret = mtk_cpufreq_voltage_tracking(info, vproc);
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else
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ret = regulator_set_voltage(info->proc_reg, vproc,
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soc_data->proc_max_volt);
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if (!ret)
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info->pre_vproc = vproc;
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return ret;
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}
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static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
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{
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struct device_link *sup_link;
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if (info->ccifreq_bound)
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return true;
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sup_link = device_link_add(info->cpu_dev, info->cci_dev,
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DL_FLAG_AUTOREMOVE_CONSUMER);
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if (!sup_link) {
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dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
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return false;
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}
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if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
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return false;
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info->ccifreq_bound = true;
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return true;
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}
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static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct cpufreq_frequency_table *freq_table = policy->freq_table;
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struct clk *cpu_clk = policy->clk;
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struct clk *armpll = clk_get_parent(cpu_clk);
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struct mtk_cpu_dvfs_info *info = policy->driver_data;
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struct device *cpu_dev = info->cpu_dev;
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struct dev_pm_opp *opp;
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long freq_hz, pre_freq_hz;
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int vproc, pre_vproc, inter_vproc, target_vproc, ret;
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inter_vproc = info->intermediate_voltage;
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pre_freq_hz = clk_get_rate(cpu_clk);
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mutex_lock(&info->reg_lock);
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if (unlikely(info->pre_vproc <= 0))
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pre_vproc = regulator_get_voltage(info->proc_reg);
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else
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pre_vproc = info->pre_vproc;
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if (pre_vproc < 0) {
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dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
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ret = pre_vproc;
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goto out;
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}
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freq_hz = freq_table[index].frequency * 1000;
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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if (IS_ERR(opp)) {
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dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
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policy->cpu, freq_hz);
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ret = PTR_ERR(opp);
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goto out;
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}
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vproc = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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/*
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* If MediaTek cci is supported but is not ready, we will use the value
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* of max(target cpu voltage, booting voltage) to prevent high freqeuncy
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* low voltage crash.
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*/
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if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
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vproc = max(vproc, info->vproc_on_boot);
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/*
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* If the new voltage or the intermediate voltage is higher than the
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* current voltage, scale up voltage first.
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*/
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target_vproc = max(inter_vproc, vproc);
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if (pre_vproc <= target_vproc) {
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ret = mtk_cpufreq_set_voltage(info, target_vproc);
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if (ret) {
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dev_err(cpu_dev,
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"cpu%d: failed to scale up voltage!\n", policy->cpu);
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mtk_cpufreq_set_voltage(info, pre_vproc);
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goto out;
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}
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}
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/* Reparent the CPU clock to intermediate clock. */
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ret = clk_set_parent(cpu_clk, info->inter_clk);
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if (ret) {
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dev_err(cpu_dev,
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"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
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mtk_cpufreq_set_voltage(info, pre_vproc);
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goto out;
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}
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/* Set the original PLL to target rate. */
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ret = clk_set_rate(armpll, freq_hz);
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if (ret) {
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dev_err(cpu_dev,
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"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
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clk_set_parent(cpu_clk, armpll);
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mtk_cpufreq_set_voltage(info, pre_vproc);
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goto out;
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}
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/* Set parent of CPU clock back to the original PLL. */
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ret = clk_set_parent(cpu_clk, armpll);
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if (ret) {
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dev_err(cpu_dev,
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"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
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mtk_cpufreq_set_voltage(info, inter_vproc);
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goto out;
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}
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/*
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* If the new voltage is lower than the intermediate voltage or the
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* original voltage, scale down to the new voltage.
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*/
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if (vproc < inter_vproc || vproc < pre_vproc) {
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ret = mtk_cpufreq_set_voltage(info, vproc);
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if (ret) {
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dev_err(cpu_dev,
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"cpu%d: failed to scale down voltage!\n", policy->cpu);
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clk_set_parent(cpu_clk, info->inter_clk);
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clk_set_rate(armpll, pre_freq_hz);
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clk_set_parent(cpu_clk, armpll);
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goto out;
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}
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}
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info->current_freq = freq_hz;
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out:
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mutex_unlock(&info->reg_lock);
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return ret;
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}
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#define DYNAMIC_POWER "dynamic-power-coefficient"
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static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct dev_pm_opp *opp = data;
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struct dev_pm_opp *new_opp;
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struct mtk_cpu_dvfs_info *info;
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unsigned long freq, volt;
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struct cpufreq_policy *policy;
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int ret = 0;
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info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
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if (event == OPP_EVENT_ADJUST_VOLTAGE) {
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freq = dev_pm_opp_get_freq(opp);
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mutex_lock(&info->reg_lock);
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if (info->current_freq == freq) {
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volt = dev_pm_opp_get_voltage(opp);
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ret = mtk_cpufreq_set_voltage(info, volt);
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if (ret)
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dev_err(info->cpu_dev,
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"failed to scale voltage: %d\n", ret);
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}
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mutex_unlock(&info->reg_lock);
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} else if (event == OPP_EVENT_DISABLE) {
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freq = dev_pm_opp_get_freq(opp);
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/* case of current opp item is disabled */
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if (info->current_freq == freq) {
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freq = 1;
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new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
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&freq);
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if (IS_ERR(new_opp)) {
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dev_err(info->cpu_dev,
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"all opp items are disabled\n");
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ret = PTR_ERR(new_opp);
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return notifier_from_errno(ret);
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}
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dev_pm_opp_put(new_opp);
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policy = cpufreq_cpu_get(info->opp_cpu);
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if (policy) {
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cpufreq_driver_target(policy, freq / 1000,
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CPUFREQ_RELATION_L);
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cpufreq_cpu_put(policy);
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}
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}
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}
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return notifier_from_errno(ret);
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}
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static struct device *of_get_cci(struct device *cpu_dev)
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{
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struct device_node *np;
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struct platform_device *pdev;
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np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
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if (IS_ERR_OR_NULL(np))
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return NULL;
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pdev = of_find_device_by_node(np);
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of_node_put(np);
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if (IS_ERR_OR_NULL(pdev))
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return NULL;
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return &pdev->dev;
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}
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static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
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{
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struct device *cpu_dev;
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struct dev_pm_opp *opp;
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unsigned long rate;
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int ret;
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cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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dev_err(cpu_dev, "failed to get cpu%d device\n", cpu);
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return -ENODEV;
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}
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info->cpu_dev = cpu_dev;
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info->ccifreq_bound = false;
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if (info->soc_data->ccifreq_supported) {
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info->cci_dev = of_get_cci(info->cpu_dev);
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if (IS_ERR_OR_NULL(info->cci_dev)) {
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ret = PTR_ERR(info->cci_dev);
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dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
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return -ENODEV;
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}
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}
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info->cpu_clk = clk_get(cpu_dev, "cpu");
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if (IS_ERR(info->cpu_clk)) {
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ret = PTR_ERR(info->cpu_clk);
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return dev_err_probe(cpu_dev, ret,
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"cpu%d: failed to get cpu clk\n", cpu);
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}
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info->inter_clk = clk_get(cpu_dev, "intermediate");
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if (IS_ERR(info->inter_clk)) {
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ret = PTR_ERR(info->inter_clk);
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dev_err_probe(cpu_dev, ret,
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"cpu%d: failed to get intermediate clk\n", cpu);
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goto out_free_resources;
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}
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info->proc_reg = regulator_get_optional(cpu_dev, "proc");
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if (IS_ERR(info->proc_reg)) {
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ret = PTR_ERR(info->proc_reg);
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dev_err_probe(cpu_dev, ret,
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"cpu%d: failed to get proc regulator\n", cpu);
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goto out_free_resources;
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}
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ret = regulator_enable(info->proc_reg);
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if (ret) {
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dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
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goto out_free_resources;
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}
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|
|
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/* Both presence and absence of sram regulator are valid cases. */
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info->sram_reg = regulator_get_optional(cpu_dev, "sram");
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if (IS_ERR(info->sram_reg)) {
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ret = PTR_ERR(info->sram_reg);
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if (ret == -EPROBE_DEFER)
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goto out_free_resources;
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info->sram_reg = NULL;
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} else {
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ret = regulator_enable(info->sram_reg);
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if (ret) {
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dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
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goto out_free_resources;
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}
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}
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|
|
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/* Get OPP-sharing information from "operating-points-v2" bindings */
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ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
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if (ret) {
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dev_err(cpu_dev,
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"cpu%d: failed to get OPP-sharing information\n", cpu);
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goto out_free_resources;
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}
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ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
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if (ret) {
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dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
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goto out_free_resources;
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}
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|
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ret = clk_prepare_enable(info->cpu_clk);
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if (ret)
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goto out_free_opp_table;
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ret = clk_prepare_enable(info->inter_clk);
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if (ret)
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goto out_disable_mux_clock;
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|
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if (info->soc_data->ccifreq_supported) {
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info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
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if (info->vproc_on_boot < 0) {
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ret = info->vproc_on_boot;
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dev_err(info->cpu_dev,
|
|
"invalid Vproc value: %d\n", info->vproc_on_boot);
|
|
goto out_disable_inter_clock;
|
|
}
|
|
}
|
|
|
|
/* Search a safe voltage for intermediate frequency. */
|
|
rate = clk_get_rate(info->inter_clk);
|
|
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
|
|
if (IS_ERR(opp)) {
|
|
dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
|
|
ret = PTR_ERR(opp);
|
|
goto out_disable_inter_clock;
|
|
}
|
|
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
|
|
dev_pm_opp_put(opp);
|
|
|
|
mutex_init(&info->reg_lock);
|
|
info->current_freq = clk_get_rate(info->cpu_clk);
|
|
|
|
info->opp_cpu = cpu;
|
|
info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
|
|
ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
|
|
if (ret) {
|
|
dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
|
|
goto out_disable_inter_clock;
|
|
}
|
|
|
|
/*
|
|
* If SRAM regulator is present, software "voltage tracking" is needed
|
|
* for this CPU power domain.
|
|
*/
|
|
info->need_voltage_tracking = (info->sram_reg != NULL);
|
|
|
|
/*
|
|
* We assume min voltage is 0 and tracking target voltage using
|
|
* min_volt_shift for each iteration.
|
|
* The vtrack_max is 3 times of expeted iteration count.
|
|
*/
|
|
info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
|
|
info->soc_data->proc_max_volt),
|
|
info->soc_data->min_volt_shift);
|
|
|
|
return 0;
|
|
|
|
out_disable_inter_clock:
|
|
clk_disable_unprepare(info->inter_clk);
|
|
|
|
out_disable_mux_clock:
|
|
clk_disable_unprepare(info->cpu_clk);
|
|
|
|
out_free_opp_table:
|
|
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
|
|
|
|
out_free_resources:
|
|
if (regulator_is_enabled(info->proc_reg))
|
|
regulator_disable(info->proc_reg);
|
|
if (info->sram_reg && regulator_is_enabled(info->sram_reg))
|
|
regulator_disable(info->sram_reg);
|
|
|
|
if (!IS_ERR(info->proc_reg))
|
|
regulator_put(info->proc_reg);
|
|
if (!IS_ERR(info->sram_reg))
|
|
regulator_put(info->sram_reg);
|
|
if (!IS_ERR(info->cpu_clk))
|
|
clk_put(info->cpu_clk);
|
|
if (!IS_ERR(info->inter_clk))
|
|
clk_put(info->inter_clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
|
|
{
|
|
if (!IS_ERR(info->proc_reg)) {
|
|
regulator_disable(info->proc_reg);
|
|
regulator_put(info->proc_reg);
|
|
}
|
|
if (!IS_ERR(info->sram_reg)) {
|
|
regulator_disable(info->sram_reg);
|
|
regulator_put(info->sram_reg);
|
|
}
|
|
if (!IS_ERR(info->cpu_clk)) {
|
|
clk_disable_unprepare(info->cpu_clk);
|
|
clk_put(info->cpu_clk);
|
|
}
|
|
if (!IS_ERR(info->inter_clk)) {
|
|
clk_disable_unprepare(info->inter_clk);
|
|
clk_put(info->inter_clk);
|
|
}
|
|
|
|
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
|
|
dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
|
|
}
|
|
|
|
static int mtk_cpufreq_init(struct cpufreq_policy *policy)
|
|
{
|
|
struct mtk_cpu_dvfs_info *info;
|
|
struct cpufreq_frequency_table *freq_table;
|
|
int ret;
|
|
|
|
info = mtk_cpu_dvfs_info_lookup(policy->cpu);
|
|
if (!info) {
|
|
pr_err("dvfs info for cpu%d is not initialized.\n",
|
|
policy->cpu);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
|
|
if (ret) {
|
|
dev_err(info->cpu_dev,
|
|
"failed to init cpufreq table for cpu%d: %d\n",
|
|
policy->cpu, ret);
|
|
return ret;
|
|
}
|
|
|
|
cpumask_copy(policy->cpus, &info->cpus);
|
|
policy->freq_table = freq_table;
|
|
policy->driver_data = info;
|
|
policy->clk = info->cpu_clk;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
|
|
{
|
|
struct mtk_cpu_dvfs_info *info = policy->driver_data;
|
|
|
|
dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct cpufreq_driver mtk_cpufreq_driver = {
|
|
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
|
|
CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
|
|
CPUFREQ_IS_COOLING_DEV,
|
|
.verify = cpufreq_generic_frequency_table_verify,
|
|
.target_index = mtk_cpufreq_set_target,
|
|
.get = cpufreq_generic_get,
|
|
.init = mtk_cpufreq_init,
|
|
.exit = mtk_cpufreq_exit,
|
|
.register_em = cpufreq_register_em_with_opp,
|
|
.name = "mtk-cpufreq",
|
|
.attr = cpufreq_generic_attr,
|
|
};
|
|
|
|
static int mtk_cpufreq_probe(struct platform_device *pdev)
|
|
{
|
|
const struct mtk_cpufreq_platform_data *data;
|
|
struct mtk_cpu_dvfs_info *info, *tmp;
|
|
int cpu, ret;
|
|
|
|
data = dev_get_platdata(&pdev->dev);
|
|
if (!data) {
|
|
dev_err(&pdev->dev,
|
|
"failed to get mtk cpufreq platform data\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
info = mtk_cpu_dvfs_info_lookup(cpu);
|
|
if (info)
|
|
continue;
|
|
|
|
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
|
|
if (!info) {
|
|
ret = -ENOMEM;
|
|
goto release_dvfs_info_list;
|
|
}
|
|
|
|
info->soc_data = data;
|
|
ret = mtk_cpu_dvfs_info_init(info, cpu);
|
|
if (ret) {
|
|
dev_err(&pdev->dev,
|
|
"failed to initialize dvfs info for cpu%d\n",
|
|
cpu);
|
|
goto release_dvfs_info_list;
|
|
}
|
|
|
|
list_add(&info->list_head, &dvfs_info_list);
|
|
}
|
|
|
|
ret = cpufreq_register_driver(&mtk_cpufreq_driver);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to register mtk cpufreq driver\n");
|
|
goto release_dvfs_info_list;
|
|
}
|
|
|
|
return 0;
|
|
|
|
release_dvfs_info_list:
|
|
list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) {
|
|
mtk_cpu_dvfs_info_release(info);
|
|
list_del(&info->list_head);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver mtk_cpufreq_platdrv = {
|
|
.driver = {
|
|
.name = "mtk-cpufreq",
|
|
},
|
|
.probe = mtk_cpufreq_probe,
|
|
};
|
|
|
|
static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
|
|
.min_volt_shift = 100000,
|
|
.max_volt_shift = 200000,
|
|
.proc_max_volt = 1150000,
|
|
.sram_min_volt = 0,
|
|
.sram_max_volt = 1150000,
|
|
.ccifreq_supported = false,
|
|
};
|
|
|
|
static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
|
|
.min_volt_shift = 100000,
|
|
.max_volt_shift = 200000,
|
|
.proc_max_volt = 1150000,
|
|
.sram_min_volt = 0,
|
|
.sram_max_volt = 1150000,
|
|
.ccifreq_supported = true,
|
|
};
|
|
|
|
static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
|
|
.min_volt_shift = 100000,
|
|
.max_volt_shift = 250000,
|
|
.proc_max_volt = 1118750,
|
|
.sram_min_volt = 850000,
|
|
.sram_max_volt = 1118750,
|
|
.ccifreq_supported = true,
|
|
};
|
|
|
|
/* List of machines supported by this driver */
|
|
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
|
|
{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
|
|
{ .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
|
|
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
|
|
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
|
|
|
|
static int __init mtk_cpufreq_driver_init(void)
|
|
{
|
|
struct device_node *np;
|
|
const struct of_device_id *match;
|
|
const struct mtk_cpufreq_platform_data *data;
|
|
int err;
|
|
|
|
np = of_find_node_by_path("/");
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
match = of_match_node(mtk_cpufreq_machines, np);
|
|
of_node_put(np);
|
|
if (!match) {
|
|
pr_debug("Machine is not compatible with mtk-cpufreq\n");
|
|
return -ENODEV;
|
|
}
|
|
data = match->data;
|
|
|
|
err = platform_driver_register(&mtk_cpufreq_platdrv);
|
|
if (err)
|
|
return err;
|
|
|
|
/*
|
|
* Since there's no place to hold device registration code and no
|
|
* device tree based way to match cpufreq driver yet, both the driver
|
|
* and the device registration codes are put here to handle defer
|
|
* probing.
|
|
*/
|
|
cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
|
|
data, sizeof(*data));
|
|
if (IS_ERR(cpufreq_pdev)) {
|
|
pr_err("failed to register mtk-cpufreq platform device\n");
|
|
platform_driver_unregister(&mtk_cpufreq_platdrv);
|
|
return PTR_ERR(cpufreq_pdev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
module_init(mtk_cpufreq_driver_init)
|
|
|
|
static void __exit mtk_cpufreq_driver_exit(void)
|
|
{
|
|
platform_device_unregister(cpufreq_pdev);
|
|
platform_driver_unregister(&mtk_cpufreq_platdrv);
|
|
}
|
|
module_exit(mtk_cpufreq_driver_exit)
|
|
|
|
MODULE_DESCRIPTION("MediaTek CPUFreq driver");
|
|
MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>");
|
|
MODULE_LICENSE("GPL v2");
|