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![Sowjanya Komatineni](/assets/img/avatar_default.png)
This patch adds suspend and resume pm ops for cpufreq driver. PLLP is the safe clock source for CPU during system suspend and resume as PLLP rate is below the CPU Fmax at Vmin. CPUFreq driver suspend switches the CPU clock source to PLLP and disables the DFLL clock. During system resume, warmboot code powers up the CPU with PLLP clock source. So CPUFreq driver resume enabled DFLL clock and switches CPU back to DFLL clock source. Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
224 lines
4.9 KiB
C
224 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra 124 cpufreq driver
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/types.h>
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struct tegra124_cpufreq_priv {
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struct clk *cpu_clk;
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struct clk *pllp_clk;
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struct clk *pllx_clk;
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struct clk *dfll_clk;
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struct platform_device *cpufreq_dt_pdev;
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};
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static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv)
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{
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struct clk *orig_parent;
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int ret;
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ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));
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if (ret)
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return ret;
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orig_parent = clk_get_parent(priv->cpu_clk);
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clk_set_parent(priv->cpu_clk, priv->pllp_clk);
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ret = clk_prepare_enable(priv->dfll_clk);
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if (ret)
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goto out;
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clk_set_parent(priv->cpu_clk, priv->dfll_clk);
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return 0;
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out:
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clk_set_parent(priv->cpu_clk, orig_parent);
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return ret;
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}
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static int tegra124_cpufreq_probe(struct platform_device *pdev)
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{
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struct tegra124_cpufreq_priv *priv;
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struct device_node *np;
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struct device *cpu_dev;
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struct platform_device_info cpufreq_dt_devinfo = {};
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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cpu_dev = get_cpu_device(0);
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if (!cpu_dev)
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return -ENODEV;
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np = of_cpu_device_node_get(0);
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if (!np)
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return -ENODEV;
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priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
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if (IS_ERR(priv->cpu_clk)) {
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ret = PTR_ERR(priv->cpu_clk);
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goto out_put_np;
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}
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priv->dfll_clk = of_clk_get_by_name(np, "dfll");
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if (IS_ERR(priv->dfll_clk)) {
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ret = PTR_ERR(priv->dfll_clk);
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goto out_put_cpu_clk;
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}
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priv->pllx_clk = of_clk_get_by_name(np, "pll_x");
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if (IS_ERR(priv->pllx_clk)) {
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ret = PTR_ERR(priv->pllx_clk);
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goto out_put_dfll_clk;
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}
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priv->pllp_clk = of_clk_get_by_name(np, "pll_p");
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if (IS_ERR(priv->pllp_clk)) {
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ret = PTR_ERR(priv->pllp_clk);
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goto out_put_pllx_clk;
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}
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ret = tegra124_cpu_switch_to_dfll(priv);
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if (ret)
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goto out_put_pllp_clk;
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cpufreq_dt_devinfo.name = "cpufreq-dt";
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cpufreq_dt_devinfo.parent = &pdev->dev;
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priv->cpufreq_dt_pdev =
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platform_device_register_full(&cpufreq_dt_devinfo);
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if (IS_ERR(priv->cpufreq_dt_pdev)) {
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ret = PTR_ERR(priv->cpufreq_dt_pdev);
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goto out_put_pllp_clk;
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}
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platform_set_drvdata(pdev, priv);
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of_node_put(np);
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return 0;
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out_put_pllp_clk:
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clk_put(priv->pllp_clk);
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out_put_pllx_clk:
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clk_put(priv->pllx_clk);
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out_put_dfll_clk:
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clk_put(priv->dfll_clk);
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out_put_cpu_clk:
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clk_put(priv->cpu_clk);
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out_put_np:
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of_node_put(np);
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return ret;
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}
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static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
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{
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struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
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int err;
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/*
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* PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
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* use during suspend and resume. So, switch the CPU clock source
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* to PLLP and disable DFLL.
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*/
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err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
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if (err < 0) {
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dev_err(dev, "failed to reparent to PLLP: %d\n", err);
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return err;
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}
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clk_disable_unprepare(priv->dfll_clk);
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return 0;
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}
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static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
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{
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struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
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int err;
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/*
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* Warmboot code powers up the CPU with PLLP clock source.
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* Enable DFLL clock and switch CPU clock source back to DFLL.
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*/
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err = clk_prepare_enable(priv->dfll_clk);
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if (err < 0) {
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dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
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goto disable_cpufreq;
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}
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err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
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if (err < 0) {
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dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
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goto disable_dfll;
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}
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return 0;
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disable_dfll:
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clk_disable_unprepare(priv->dfll_clk);
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disable_cpufreq:
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disable_cpufreq();
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return err;
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}
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static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
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tegra124_cpufreq_resume)
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};
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static struct platform_driver tegra124_cpufreq_platdrv = {
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.driver.name = "cpufreq-tegra124",
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.driver.pm = &tegra124_cpufreq_pm_ops,
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.probe = tegra124_cpufreq_probe,
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};
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static int __init tegra_cpufreq_init(void)
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{
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int ret;
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struct platform_device *pdev;
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if (!(of_machine_is_compatible("nvidia,tegra124") ||
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of_machine_is_compatible("nvidia,tegra210")))
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return -ENODEV;
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/*
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* Platform driver+device required for handling EPROBE_DEFER with
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* the regulator and the DFLL clock
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*/
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ret = platform_driver_register(&tegra124_cpufreq_platdrv);
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if (ret)
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return ret;
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pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
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if (IS_ERR(pdev)) {
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platform_driver_unregister(&tegra124_cpufreq_platdrv);
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return PTR_ERR(pdev);
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}
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return 0;
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}
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module_init(tegra_cpufreq_init);
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MODULE_AUTHOR("Tuomas Tynkkynen <ttynkkynen@nvidia.com>");
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MODULE_DESCRIPTION("cpufreq driver for NVIDIA Tegra124");
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MODULE_LICENSE("GPL v2");
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