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![Krzysztof Kozlowski](/assets/img/avatar_default.png)
Use devm_platform_ioremap_resource_byname() instead of platform_get_resource_byname() and devm_ioremap_resource(). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220419142859.380566-6-krzysztof.kozlowski@linaro.org
946 lines
25 KiB
C
946 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
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*
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* Copyright (c) 2017 Broadcom
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*/
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/*
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* This driver provides access to the DPFE interface of Broadcom STB SoCs.
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* The firmware running on the DCPU inside the DDR PHY can provide current
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* information about the system's RAM, for instance the DRAM refresh rate.
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* This can be used as an indirect indicator for the DRAM's temperature.
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* Slower refresh rate means cooler RAM, higher refresh rate means hotter
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* RAM.
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*
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* Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
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* already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
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*
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* Note regarding the loading of the firmware image: we use be32_to_cpu()
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* and le_32_to_cpu(), so we can support the following four cases:
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* - LE kernel + LE firmware image (the most common case)
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* - LE kernel + BE firmware image
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* - BE kernel + LE firmware image
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* - BE kernel + BE firmware image
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*
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* The DPCU always runs in big endian mode. The firmware image, however, can
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* be in either format. Also, communication between host CPU and DCPU is
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* always in little endian.
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*/
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#define DRVNAME "brcmstb-dpfe"
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/* DCPU register offsets */
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#define REG_DCPU_RESET 0x0
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#define REG_TO_DCPU_MBOX 0x10
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#define REG_TO_HOST_MBOX 0x14
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/* Macros to process offsets returned by the DCPU */
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#define DRAM_MSG_ADDR_OFFSET 0x0
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#define DRAM_MSG_TYPE_OFFSET 0x1c
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#define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
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#define DRAM_MSG_TYPE_MASK ((1UL << \
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(BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
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/* Message RAM */
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#define DCPU_MSG_RAM_START 0x100
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#define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32))
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/* DRAM Info Offsets & Masks */
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#define DRAM_INFO_INTERVAL 0x0
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#define DRAM_INFO_MR4 0x4
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#define DRAM_INFO_ERROR 0x8
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#define DRAM_INFO_MR4_MASK 0xff
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#define DRAM_INFO_MR4_SHIFT 24 /* We need to look at byte 3 */
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/* DRAM MR4 Offsets & Masks */
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#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */
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#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */
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#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */
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#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */
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#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */
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#define DRAM_MR4_REFRESH_MASK 0x7
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#define DRAM_MR4_SR_ABORT_MASK 0x1
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#define DRAM_MR4_PPRE_MASK 0x1
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#define DRAM_MR4_TH_OFFS_MASK 0x3
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#define DRAM_MR4_TUF_MASK 0x1
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/* DRAM Vendor Offsets & Masks (API v2) */
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#define DRAM_VENDOR_MR5 0x0
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#define DRAM_VENDOR_MR6 0x4
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#define DRAM_VENDOR_MR7 0x8
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#define DRAM_VENDOR_MR8 0xc
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#define DRAM_VENDOR_ERROR 0x10
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#define DRAM_VENDOR_MASK 0xff
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#define DRAM_VENDOR_SHIFT 24 /* We need to look at byte 3 */
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/* DRAM Information Offsets & Masks (API v3) */
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#define DRAM_DDR_INFO_MR4 0x0
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#define DRAM_DDR_INFO_MR5 0x4
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#define DRAM_DDR_INFO_MR6 0x8
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#define DRAM_DDR_INFO_MR7 0xc
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#define DRAM_DDR_INFO_MR8 0x10
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#define DRAM_DDR_INFO_ERROR 0x14
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#define DRAM_DDR_INFO_MASK 0xff
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/* Reset register bits & masks */
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#define DCPU_RESET_SHIFT 0x0
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#define DCPU_RESET_MASK 0x1
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#define DCPU_CLK_DISABLE_SHIFT 0x2
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/* DCPU return codes */
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#define DCPU_RET_ERROR_BIT BIT(31)
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#define DCPU_RET_SUCCESS 0x1
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#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0))
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#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1))
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#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2))
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#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3))
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/* This error code is not firmware defined and only used in the driver. */
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#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4))
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/* Firmware magic */
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#define DPFE_BE_MAGIC 0xfe1010fe
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#define DPFE_LE_MAGIC 0xfe0101fe
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/* Error codes */
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#define ERR_INVALID_MAGIC -1
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#define ERR_INVALID_SIZE -2
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#define ERR_INVALID_CHKSUM -3
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/* Message types */
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#define DPFE_MSG_TYPE_COMMAND 1
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#define DPFE_MSG_TYPE_RESPONSE 2
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#define DELAY_LOOP_MAX 1000
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enum dpfe_msg_fields {
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MSG_HEADER,
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MSG_COMMAND,
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MSG_ARG_COUNT,
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MSG_ARG0,
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MSG_FIELD_MAX = 16 /* Max number of arguments */
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};
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enum dpfe_commands {
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DPFE_CMD_GET_INFO,
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DPFE_CMD_GET_REFRESH,
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DPFE_CMD_GET_VENDOR,
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DPFE_CMD_MAX /* Last entry */
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};
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/*
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* Format of the binary firmware file:
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*
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* entry
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* 0 header
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* value: 0xfe0101fe <== little endian
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* 0xfe1010fe <== big endian
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* 1 sequence:
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* [31:16] total segments on this build
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* [15:0] this segment sequence.
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* 2 FW version
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* 3 IMEM byte size
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* 4 DMEM byte size
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* IMEM
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* DMEM
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* last checksum ==> sum of everything
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*/
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struct dpfe_firmware_header {
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u32 magic;
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u32 sequence;
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u32 version;
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u32 imem_size;
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u32 dmem_size;
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};
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/* Things we only need during initialization. */
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struct init_data {
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unsigned int dmem_len;
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unsigned int imem_len;
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unsigned int chksum;
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bool is_big_endian;
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};
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/* API version and corresponding commands */
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struct dpfe_api {
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int version;
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const char *fw_name;
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const struct attribute_group **sysfs_attrs;
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u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
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};
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/* Things we need for as long as we are active. */
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struct brcmstb_dpfe_priv {
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void __iomem *regs;
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void __iomem *dmem;
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void __iomem *imem;
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struct device *dev;
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const struct dpfe_api *dpfe_api;
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struct mutex lock;
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};
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/*
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* Forward declaration of our sysfs attribute functions, so we can declare the
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* attribute data structures early.
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*/
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static ssize_t show_info(struct device *, struct device_attribute *, char *);
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static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
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static ssize_t store_refresh(struct device *, struct device_attribute *,
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const char *, size_t);
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static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
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static ssize_t show_dram(struct device *, struct device_attribute *, char *);
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/*
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* Declare our attributes early, so they can be referenced in the API data
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* structure. We need to do this, because the attributes depend on the API
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* version.
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*/
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static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
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static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
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static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
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static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
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/* API v2 sysfs attributes */
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static struct attribute *dpfe_v2_attrs[] = {
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&dev_attr_dpfe_info.attr,
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&dev_attr_dpfe_refresh.attr,
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&dev_attr_dpfe_vendor.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(dpfe_v2);
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/* API v3 sysfs attributes */
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static struct attribute *dpfe_v3_attrs[] = {
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&dev_attr_dpfe_info.attr,
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&dev_attr_dpfe_dram.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(dpfe_v3);
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/*
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* Old API v2 firmware commands, as defined in the rev 0.61 specification, we
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* use a version set to 1 to denote that it is not compatible with the new API
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* v2 and onwards.
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*/
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static const struct dpfe_api dpfe_api_old_v2 = {
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.version = 1,
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.fw_name = "dpfe.bin",
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.sysfs_attrs = dpfe_v2_groups,
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.command = {
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[DPFE_CMD_GET_INFO] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 1,
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[MSG_ARG_COUNT] = 1,
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[MSG_ARG0] = 1,
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},
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[DPFE_CMD_GET_REFRESH] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 2,
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[MSG_ARG_COUNT] = 1,
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[MSG_ARG0] = 1,
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},
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[DPFE_CMD_GET_VENDOR] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 2,
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[MSG_ARG_COUNT] = 1,
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[MSG_ARG0] = 2,
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},
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}
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};
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/*
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* API v2 firmware commands, as defined in the rev 0.8 specification, named new
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* v2 here
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*/
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static const struct dpfe_api dpfe_api_new_v2 = {
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.version = 2,
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.fw_name = NULL, /* We expect the firmware to have been downloaded! */
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.sysfs_attrs = dpfe_v2_groups,
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.command = {
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[DPFE_CMD_GET_INFO] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 0x101,
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},
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[DPFE_CMD_GET_REFRESH] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 0x201,
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},
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[DPFE_CMD_GET_VENDOR] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 0x202,
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},
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}
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};
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/* API v3 firmware commands */
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static const struct dpfe_api dpfe_api_v3 = {
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.version = 3,
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.fw_name = NULL, /* We expect the firmware to have been downloaded! */
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.sysfs_attrs = dpfe_v3_groups,
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.command = {
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[DPFE_CMD_GET_INFO] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 0x0101,
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[MSG_ARG_COUNT] = 1,
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[MSG_ARG0] = 1,
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},
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[DPFE_CMD_GET_REFRESH] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 0x0202,
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[MSG_ARG_COUNT] = 0,
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},
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/* There's no GET_VENDOR command in API v3. */
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},
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};
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static const char *get_error_text(unsigned int i)
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{
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static const char * const error_text[] = {
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"Success", "Header code incorrect",
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"Unknown command or argument", "Incorrect checksum",
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"Malformed command", "Timed out", "Unknown error",
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};
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if (unlikely(i >= ARRAY_SIZE(error_text)))
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i = ARRAY_SIZE(error_text) - 1;
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return error_text[i];
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}
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static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv)
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{
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u32 val;
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mutex_lock(&priv->lock);
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val = readl_relaxed(priv->regs + REG_DCPU_RESET);
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mutex_unlock(&priv->lock);
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return !(val & DCPU_RESET_MASK);
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}
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static void __disable_dcpu(struct brcmstb_dpfe_priv *priv)
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{
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u32 val;
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if (!is_dcpu_enabled(priv))
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return;
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mutex_lock(&priv->lock);
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/* Put DCPU in reset if it's running. */
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val = readl_relaxed(priv->regs + REG_DCPU_RESET);
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val |= (1 << DCPU_RESET_SHIFT);
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writel_relaxed(val, priv->regs + REG_DCPU_RESET);
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mutex_unlock(&priv->lock);
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}
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static void __enable_dcpu(struct brcmstb_dpfe_priv *priv)
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{
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void __iomem *regs = priv->regs;
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u32 val;
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mutex_lock(&priv->lock);
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/* Clear mailbox registers. */
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writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
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writel_relaxed(0, regs + REG_TO_HOST_MBOX);
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/* Disable DCPU clock gating */
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val = readl_relaxed(regs + REG_DCPU_RESET);
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val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
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writel_relaxed(val, regs + REG_DCPU_RESET);
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/* Take DCPU out of reset */
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val = readl_relaxed(regs + REG_DCPU_RESET);
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val &= ~(1 << DCPU_RESET_SHIFT);
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writel_relaxed(val, regs + REG_DCPU_RESET);
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mutex_unlock(&priv->lock);
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}
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static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
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{
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unsigned int sum = 0;
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unsigned int i;
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/* Don't include the last field in the checksum. */
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for (i = 0; i < max; i++)
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sum += msg[i];
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return sum;
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}
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static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response,
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char *buf, ssize_t *size)
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{
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unsigned int msg_type;
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unsigned int offset;
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void __iomem *ptr = NULL;
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/* There is no need to use this function for API v3 or later. */
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if (unlikely(priv->dpfe_api->version >= 3))
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return NULL;
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msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
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offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
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/*
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* msg_type == 1: the offset is relative to the message RAM
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* msg_type == 0: the offset is relative to the data RAM (this is the
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* previous way of passing data)
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* msg_type is anything else: there's critical hardware problem
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*/
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switch (msg_type) {
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case 1:
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ptr = priv->regs + DCPU_MSG_RAM_START + offset;
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break;
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case 0:
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ptr = priv->dmem + offset;
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break;
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default:
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dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
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response);
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if (buf && size)
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*size = sprintf(buf,
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"FATAL: communication error with DCPU\n");
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}
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return ptr;
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}
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static void __finalize_command(struct brcmstb_dpfe_priv *priv)
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{
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unsigned int release_mbox;
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/*
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* It depends on the API version which MBOX register we have to write to
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* signal we are done.
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*/
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release_mbox = (priv->dpfe_api->version < 2)
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? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
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writel_relaxed(0, priv->regs + release_mbox);
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}
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static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd,
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u32 result[])
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{
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const u32 *msg = priv->dpfe_api->command[cmd];
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void __iomem *regs = priv->regs;
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unsigned int i, chksum, chksum_idx;
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int ret = 0;
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u32 resp;
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if (cmd >= DPFE_CMD_MAX)
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return -1;
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mutex_lock(&priv->lock);
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/* Wait for DCPU to become ready */
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for (i = 0; i < DELAY_LOOP_MAX; i++) {
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resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
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if (resp == 0)
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break;
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msleep(1);
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}
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if (resp != 0) {
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mutex_unlock(&priv->lock);
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return -ffs(DCPU_RET_ERR_TIMEDOUT);
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}
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/* Compute checksum over the message */
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chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
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chksum = get_msg_chksum(msg, chksum_idx);
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/* Write command and arguments to message area */
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for (i = 0; i < MSG_FIELD_MAX; i++) {
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if (i == chksum_idx)
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writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
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else
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writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
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}
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/* Tell DCPU there is a command waiting */
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writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
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/* Wait for DCPU to process the command */
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for (i = 0; i < DELAY_LOOP_MAX; i++) {
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/* Read response code */
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resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
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if (resp > 0)
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break;
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msleep(1);
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}
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if (i == DELAY_LOOP_MAX) {
|
|
resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
|
|
ret = -ffs(resp);
|
|
} else {
|
|
/* Read response data */
|
|
for (i = 0; i < MSG_FIELD_MAX; i++)
|
|
result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
|
|
chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
|
|
}
|
|
|
|
/* Tell DCPU we are done */
|
|
__finalize_command(priv);
|
|
|
|
mutex_unlock(&priv->lock);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Verify response */
|
|
chksum = get_msg_chksum(result, chksum_idx);
|
|
if (chksum != result[chksum_idx])
|
|
resp = DCPU_RET_ERR_CHKSUM;
|
|
|
|
if (resp != DCPU_RET_SUCCESS) {
|
|
resp &= ~DCPU_RET_ERROR_BIT;
|
|
ret = -ffs(resp);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Ensure that the firmware file loaded meets all the requirements. */
|
|
static int __verify_firmware(struct init_data *init,
|
|
const struct firmware *fw)
|
|
{
|
|
const struct dpfe_firmware_header *header = (void *)fw->data;
|
|
unsigned int dmem_size, imem_size, total_size;
|
|
bool is_big_endian = false;
|
|
const u32 *chksum_ptr;
|
|
|
|
if (header->magic == DPFE_BE_MAGIC)
|
|
is_big_endian = true;
|
|
else if (header->magic != DPFE_LE_MAGIC)
|
|
return ERR_INVALID_MAGIC;
|
|
|
|
if (is_big_endian) {
|
|
dmem_size = be32_to_cpu(header->dmem_size);
|
|
imem_size = be32_to_cpu(header->imem_size);
|
|
} else {
|
|
dmem_size = le32_to_cpu(header->dmem_size);
|
|
imem_size = le32_to_cpu(header->imem_size);
|
|
}
|
|
|
|
/* Data and instruction sections are 32 bit words. */
|
|
if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
|
|
return ERR_INVALID_SIZE;
|
|
|
|
/*
|
|
* The header + the data section + the instruction section + the
|
|
* checksum must be equal to the total firmware size.
|
|
*/
|
|
total_size = dmem_size + imem_size + sizeof(*header) +
|
|
sizeof(*chksum_ptr);
|
|
if (total_size != fw->size)
|
|
return ERR_INVALID_SIZE;
|
|
|
|
/* The checksum comes at the very end. */
|
|
chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
|
|
|
|
init->is_big_endian = is_big_endian;
|
|
init->dmem_len = dmem_size;
|
|
init->imem_len = imem_size;
|
|
init->chksum = (is_big_endian)
|
|
? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Verify checksum by reading back the firmware from co-processor RAM. */
|
|
static int __verify_fw_checksum(struct init_data *init,
|
|
struct brcmstb_dpfe_priv *priv,
|
|
const struct dpfe_firmware_header *header,
|
|
u32 checksum)
|
|
{
|
|
u32 magic, sequence, version, sum;
|
|
u32 __iomem *dmem = priv->dmem;
|
|
u32 __iomem *imem = priv->imem;
|
|
unsigned int i;
|
|
|
|
if (init->is_big_endian) {
|
|
magic = be32_to_cpu(header->magic);
|
|
sequence = be32_to_cpu(header->sequence);
|
|
version = be32_to_cpu(header->version);
|
|
} else {
|
|
magic = le32_to_cpu(header->magic);
|
|
sequence = le32_to_cpu(header->sequence);
|
|
version = le32_to_cpu(header->version);
|
|
}
|
|
|
|
sum = magic + sequence + version + init->dmem_len + init->imem_len;
|
|
|
|
for (i = 0; i < init->dmem_len / sizeof(u32); i++)
|
|
sum += readl_relaxed(dmem + i);
|
|
|
|
for (i = 0; i < init->imem_len / sizeof(u32); i++)
|
|
sum += readl_relaxed(imem + i);
|
|
|
|
return (sum == checksum) ? 0 : -1;
|
|
}
|
|
|
|
static int __write_firmware(u32 __iomem *mem, const u32 *fw,
|
|
unsigned int size, bool is_big_endian)
|
|
{
|
|
unsigned int i;
|
|
|
|
/* Convert size to 32-bit words. */
|
|
size /= sizeof(u32);
|
|
|
|
/* It is recommended to clear the firmware area first. */
|
|
for (i = 0; i < size; i++)
|
|
writel_relaxed(0, mem + i);
|
|
|
|
/* Now copy it. */
|
|
if (is_big_endian) {
|
|
for (i = 0; i < size; i++)
|
|
writel_relaxed(be32_to_cpu(fw[i]), mem + i);
|
|
} else {
|
|
for (i = 0; i < size; i++)
|
|
writel_relaxed(le32_to_cpu(fw[i]), mem + i);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv)
|
|
{
|
|
const struct dpfe_firmware_header *header;
|
|
unsigned int dmem_size, imem_size;
|
|
struct device *dev = priv->dev;
|
|
bool is_big_endian = false;
|
|
const struct firmware *fw;
|
|
const u32 *dmem, *imem;
|
|
struct init_data init;
|
|
const void *fw_blob;
|
|
int ret;
|
|
|
|
/*
|
|
* Skip downloading the firmware if the DCPU is already running and
|
|
* responding to commands.
|
|
*/
|
|
if (is_dcpu_enabled(priv)) {
|
|
u32 response[MSG_FIELD_MAX];
|
|
|
|
ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
|
|
if (!ret)
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* If the firmware filename is NULL it means the boot firmware has to
|
|
* download the DCPU firmware for us. If that didn't work, we have to
|
|
* bail, since downloading it ourselves wouldn't work either.
|
|
*/
|
|
if (!priv->dpfe_api->fw_name)
|
|
return -ENODEV;
|
|
|
|
ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev);
|
|
/*
|
|
* Defer the firmware download if the firmware file couldn't be found.
|
|
* The root file system may not be available yet.
|
|
*/
|
|
if (ret)
|
|
return (ret == -ENOENT) ? -EPROBE_DEFER : ret;
|
|
|
|
ret = __verify_firmware(&init, fw);
|
|
if (ret) {
|
|
ret = -EFAULT;
|
|
goto release_fw;
|
|
}
|
|
|
|
__disable_dcpu(priv);
|
|
|
|
is_big_endian = init.is_big_endian;
|
|
dmem_size = init.dmem_len;
|
|
imem_size = init.imem_len;
|
|
|
|
/* At the beginning of the firmware blob is a header. */
|
|
header = (struct dpfe_firmware_header *)fw->data;
|
|
/* Void pointer to the beginning of the actual firmware. */
|
|
fw_blob = fw->data + sizeof(*header);
|
|
/* IMEM comes right after the header. */
|
|
imem = fw_blob;
|
|
/* DMEM follows after IMEM. */
|
|
dmem = fw_blob + imem_size;
|
|
|
|
ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
|
|
if (ret)
|
|
goto release_fw;
|
|
ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
|
|
if (ret)
|
|
goto release_fw;
|
|
|
|
ret = __verify_fw_checksum(&init, priv, header, init.chksum);
|
|
if (ret)
|
|
goto release_fw;
|
|
|
|
__enable_dcpu(priv);
|
|
|
|
release_fw:
|
|
release_firmware(fw);
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t generic_show(unsigned int command, u32 response[],
|
|
struct brcmstb_dpfe_priv *priv, char *buf)
|
|
{
|
|
int ret;
|
|
|
|
if (!priv)
|
|
return sprintf(buf, "ERROR: driver private data not set\n");
|
|
|
|
ret = __send_command(priv, command, response);
|
|
if (ret < 0)
|
|
return sprintf(buf, "ERROR: %s\n", get_error_text(-ret));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
|
|
char *buf)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
struct brcmstb_dpfe_priv *priv;
|
|
unsigned int info;
|
|
ssize_t ret;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info = response[MSG_ARG0];
|
|
|
|
return sprintf(buf, "%u.%u.%u.%u\n",
|
|
(info >> 24) & 0xff,
|
|
(info >> 16) & 0xff,
|
|
(info >> 8) & 0xff,
|
|
info & 0xff);
|
|
}
|
|
|
|
static ssize_t show_refresh(struct device *dev,
|
|
struct device_attribute *devattr, char *buf)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
void __iomem *info;
|
|
struct brcmstb_dpfe_priv *priv;
|
|
u8 refresh, sr_abort, ppre, thermal_offs, tuf;
|
|
u32 mr4;
|
|
ssize_t ret;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
|
|
if (!info)
|
|
return ret;
|
|
|
|
mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
|
|
DRAM_INFO_MR4_MASK;
|
|
|
|
refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
|
|
sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
|
|
ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
|
|
thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
|
|
tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
|
|
|
|
return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
|
|
readl_relaxed(info + DRAM_INFO_INTERVAL),
|
|
refresh, sr_abort, ppre, thermal_offs, tuf,
|
|
readl_relaxed(info + DRAM_INFO_ERROR));
|
|
}
|
|
|
|
static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
struct brcmstb_dpfe_priv *priv;
|
|
void __iomem *info;
|
|
unsigned long val;
|
|
int ret;
|
|
|
|
if (kstrtoul(buf, 0, &val) < 0)
|
|
return -EINVAL;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
|
|
if (!info)
|
|
return -EIO;
|
|
|
|
writel_relaxed(val, info + DRAM_INFO_INTERVAL);
|
|
|
|
return count;
|
|
}
|
|
|
|
static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
|
|
char *buf)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
struct brcmstb_dpfe_priv *priv;
|
|
void __iomem *info;
|
|
ssize_t ret;
|
|
u32 mr5, mr6, mr7, mr8, err;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
|
|
if (!info)
|
|
return ret;
|
|
|
|
mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
|
|
DRAM_VENDOR_MASK;
|
|
mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
|
|
DRAM_VENDOR_MASK;
|
|
mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
|
|
DRAM_VENDOR_MASK;
|
|
mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
|
|
DRAM_VENDOR_MASK;
|
|
err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
|
|
|
|
return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
|
|
}
|
|
|
|
static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
|
|
char *buf)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
struct brcmstb_dpfe_priv *priv;
|
|
ssize_t ret;
|
|
u32 mr4, mr5, mr6, mr7, mr8, err;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
|
|
mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
|
|
mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
|
|
mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
|
|
mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
|
|
err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
|
|
|
|
return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
|
|
mr8, err);
|
|
}
|
|
|
|
static int brcmstb_dpfe_resume(struct platform_device *pdev)
|
|
{
|
|
struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev);
|
|
|
|
return brcmstb_dpfe_download_firmware(priv);
|
|
}
|
|
|
|
static int brcmstb_dpfe_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct brcmstb_dpfe_priv *priv;
|
|
int ret;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->dev = dev;
|
|
|
|
mutex_init(&priv->lock);
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
priv->regs = devm_platform_ioremap_resource_byname(pdev, "dpfe-cpu");
|
|
if (IS_ERR(priv->regs)) {
|
|
dev_err(dev, "couldn't map DCPU registers\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
priv->dmem = devm_platform_ioremap_resource_byname(pdev, "dpfe-dmem");
|
|
if (IS_ERR(priv->dmem)) {
|
|
dev_err(dev, "Couldn't map DCPU data memory\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
priv->imem = devm_platform_ioremap_resource_byname(pdev, "dpfe-imem");
|
|
if (IS_ERR(priv->imem)) {
|
|
dev_err(dev, "Couldn't map DCPU instruction memory\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
priv->dpfe_api = of_device_get_match_data(dev);
|
|
if (unlikely(!priv->dpfe_api)) {
|
|
/*
|
|
* It should be impossible to end up here, but to be safe we
|
|
* check anyway.
|
|
*/
|
|
dev_err(dev, "Couldn't determine API\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
ret = brcmstb_dpfe_download_firmware(priv);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Couldn't download firmware\n");
|
|
|
|
ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
|
|
if (!ret)
|
|
dev_info(dev, "registered with API v%d.\n",
|
|
priv->dpfe_api->version);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int brcmstb_dpfe_remove(struct platform_device *pdev)
|
|
{
|
|
struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev);
|
|
|
|
sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id brcmstb_dpfe_of_match[] = {
|
|
/* Use legacy API v2 for a select number of chips */
|
|
{ .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_old_v2 },
|
|
{ .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_old_v2 },
|
|
{ .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_old_v2 },
|
|
{ .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_new_v2 },
|
|
/* API v3 is the default going forward */
|
|
{ .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
|
|
|
|
static struct platform_driver brcmstb_dpfe_driver = {
|
|
.driver = {
|
|
.name = DRVNAME,
|
|
.of_match_table = brcmstb_dpfe_of_match,
|
|
},
|
|
.probe = brcmstb_dpfe_probe,
|
|
.remove = brcmstb_dpfe_remove,
|
|
.resume = brcmstb_dpfe_resume,
|
|
};
|
|
|
|
module_platform_driver(brcmstb_dpfe_driver);
|
|
|
|
MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
|
|
MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
|
|
MODULE_LICENSE("GPL");
|