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![Heiner Kallweit](/assets/img/avatar_default.png)
Deasserting the reset is vital, therefore bail out in case of error. Suggested-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/b2131908-0110-006b-862f-080517f3e2d8@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
182 lines
4.7 KiB
C
182 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2L USBPHY control driver
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*
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* Copyright (C) 2021 Renesas Electronics Corporation
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/reset-controller.h>
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#define RESET 0x000
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#define RESET_SEL_PLLRESET BIT(12)
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#define RESET_PLLRESET BIT(8)
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#define RESET_SEL_P2RESET BIT(5)
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#define RESET_SEL_P1RESET BIT(4)
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#define RESET_PHYRST_2 BIT(1)
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#define RESET_PHYRST_1 BIT(0)
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#define PHY_RESET_PORT2 (RESET_SEL_P2RESET | RESET_PHYRST_2)
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#define PHY_RESET_PORT1 (RESET_SEL_P1RESET | RESET_PHYRST_1)
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#define NUM_PORTS 2
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struct rzg2l_usbphy_ctrl_priv {
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struct reset_controller_dev rcdev;
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struct reset_control *rstc;
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void __iomem *base;
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spinlock_t lock;
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};
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#define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rcdev)
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static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
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u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2;
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void __iomem *base = priv->base;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&priv->lock, flags);
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val = readl(base + RESET);
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val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
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if (port_mask == (val & port_mask))
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val |= RESET_PLLRESET;
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writel(val, base + RESET);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
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void __iomem *base = priv->base;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&priv->lock, flags);
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val = readl(base + RESET);
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val |= RESET_SEL_PLLRESET;
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val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1));
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writel(val, base + RESET);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
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u32 port_mask;
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port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
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return !!(readl(priv->base + RESET) & port_mask);
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}
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static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
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{ .compatible = "renesas,rzg2l-usbphy-ctrl" },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
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static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = {
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.assert = rzg2l_usbphy_ctrl_assert,
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.deassert = rzg2l_usbphy_ctrl_deassert,
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.status = rzg2l_usbphy_ctrl_status,
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};
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static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rzg2l_usbphy_ctrl_priv *priv;
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unsigned long flags;
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int error;
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u32 val;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(priv->rstc))
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return dev_err_probe(dev, PTR_ERR(priv->rstc),
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"failed to get reset\n");
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error = reset_control_deassert(priv->rstc);
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if (error)
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return error;
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priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops;
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priv->rcdev.of_reset_n_cells = 1;
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priv->rcdev.nr_resets = NUM_PORTS;
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priv->rcdev.of_node = dev->of_node;
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priv->rcdev.dev = dev;
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error = devm_reset_controller_register(dev, &priv->rcdev);
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if (error)
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return error;
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spin_lock_init(&priv->lock);
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dev_set_drvdata(dev, priv);
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pm_runtime_enable(&pdev->dev);
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error = pm_runtime_resume_and_get(&pdev->dev);
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if (error < 0) {
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pm_runtime_disable(&pdev->dev);
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reset_control_assert(priv->rstc);
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return dev_err_probe(&pdev->dev, error, "pm_runtime_resume_and_get failed");
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}
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/* put pll and phy into reset state */
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spin_lock_irqsave(&priv->lock, flags);
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val = readl(priv->base + RESET);
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val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1;
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writel(val, priv->base + RESET);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int rzg2l_usbphy_ctrl_remove(struct platform_device *pdev)
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{
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struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev);
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pm_runtime_put(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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reset_control_assert(priv->rstc);
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return 0;
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}
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static struct platform_driver rzg2l_usbphy_ctrl_driver = {
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.driver = {
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.name = "rzg2l_usbphy_ctrl",
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.of_match_table = rzg2l_usbphy_ctrl_match_table,
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},
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.probe = rzg2l_usbphy_ctrl_probe,
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.remove = rzg2l_usbphy_ctrl_remove,
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};
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module_platform_driver(rzg2l_usbphy_ctrl_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
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MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
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