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![Linus Walleij](/assets/img/avatar_default.png)
Implement watchdog restart in the IXP4xx watchdog timer. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220206230028.476659-1-linus.walleij@linaro.org Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
187 lines
4.9 KiB
C
187 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* drivers/char/watchdog/ixp4xx_wdt.c
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*
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* Watchdog driver for Intel IXP4xx network processors
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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* Author: Linus Walleij <linus.walleij@linaro.org>
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*
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* Copyright 2004 (c) MontaVista, Software, Inc.
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* Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/watchdog.h>
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#include <linux/bits.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/soc/ixp4xx/cpu.h>
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struct ixp4xx_wdt {
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struct watchdog_device wdd;
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void __iomem *base;
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unsigned long rate;
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};
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/* Fallback if we do not have a clock for this */
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#define IXP4XX_TIMER_FREQ 66666000
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/* Registers after the timer registers */
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#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
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#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
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#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
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#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
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#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
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#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
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#define IXP4XX_WDT_KEY 0x0000482E
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#define IXP4XX_WDT_RESET_ENABLE 0x00000001
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#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
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#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
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static inline
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struct ixp4xx_wdt *to_ixp4xx_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct ixp4xx_wdt, wdd);
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}
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static int ixp4xx_wdt_start(struct watchdog_device *wdd)
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{
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struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
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__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
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__raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
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__raw_writel(wdd->timeout * iwdt->rate,
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iwdt->base + IXP4XX_OSWT_OFFSET);
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__raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
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iwdt->base + IXP4XX_OSWE_OFFSET);
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__raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
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return 0;
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}
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static int ixp4xx_wdt_stop(struct watchdog_device *wdd)
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{
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struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
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__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
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__raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
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__raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
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return 0;
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}
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static int ixp4xx_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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wdd->timeout = timeout;
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if (watchdog_active(wdd))
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ixp4xx_wdt_start(wdd);
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return 0;
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}
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static int ixp4xx_wdt_restart(struct watchdog_device *wdd,
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unsigned long action, void *data)
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{
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struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
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__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
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__raw_writel(0, iwdt->base + IXP4XX_OSWT_OFFSET);
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__raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
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iwdt->base + IXP4XX_OSWE_OFFSET);
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return 0;
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}
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static const struct watchdog_ops ixp4xx_wdt_ops = {
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.start = ixp4xx_wdt_start,
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.stop = ixp4xx_wdt_stop,
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.set_timeout = ixp4xx_wdt_set_timeout,
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.restart = ixp4xx_wdt_restart,
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.owner = THIS_MODULE,
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};
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static const struct watchdog_info ixp4xx_wdt_info = {
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.options = WDIOF_KEEPALIVEPING
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| WDIOF_MAGICCLOSE
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| WDIOF_SETTIMEOUT,
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.identity = KBUILD_MODNAME,
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};
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/* Devres-handled clock disablement */
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static void ixp4xx_clock_action(void *d)
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{
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clk_disable_unprepare(d);
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}
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static int ixp4xx_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ixp4xx_wdt *iwdt;
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struct clk *clk;
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int ret;
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if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
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dev_err(dev, "Rev. A0 IXP42x CPU detected - watchdog disabled\n");
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return -ENODEV;
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}
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iwdt = devm_kzalloc(dev, sizeof(*iwdt), GFP_KERNEL);
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if (!iwdt)
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return -ENOMEM;
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iwdt->base = (void __iomem *)dev->platform_data;
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/*
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* Retrieve rate from a fixed clock from the device tree if
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* the parent has that, else use the default clock rate.
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*/
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clk = devm_clk_get(dev->parent, NULL);
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if (!IS_ERR(clk)) {
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, ixp4xx_clock_action, clk);
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if (ret)
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return ret;
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iwdt->rate = clk_get_rate(clk);
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}
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if (!iwdt->rate)
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iwdt->rate = IXP4XX_TIMER_FREQ;
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iwdt->wdd.info = &ixp4xx_wdt_info;
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iwdt->wdd.ops = &ixp4xx_wdt_ops;
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iwdt->wdd.min_timeout = 1;
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iwdt->wdd.max_timeout = U32_MAX / iwdt->rate;
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iwdt->wdd.parent = dev;
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/* Default to 60 seconds */
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iwdt->wdd.timeout = 60U;
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watchdog_init_timeout(&iwdt->wdd, 0, dev);
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if (__raw_readl(iwdt->base + IXP4XX_OSST_OFFSET) &
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IXP4XX_OSST_TIMER_WARM_RESET)
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iwdt->wdd.bootstatus = WDIOF_CARDRESET;
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ret = devm_watchdog_register_device(dev, &iwdt->wdd);
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if (ret)
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return ret;
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dev_info(dev, "IXP4xx watchdog available\n");
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return 0;
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}
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static struct platform_driver ixp4xx_wdt_driver = {
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.probe = ixp4xx_wdt_probe,
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.driver = {
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.name = "ixp4xx-watchdog",
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},
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};
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module_platform_driver(ixp4xx_wdt_driver);
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MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
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MODULE_DESCRIPTION("IXP4xx Network Processor Watchdog");
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MODULE_LICENSE("GPL");
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