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6620f45ff8
The vid_pll_div is a programmable fractional divider, but vendor gives a
limited of known configuration value and it's corresponding fraction.
Thus when at reset value (0) or unknown value, we cannot determine the
result rate.
The initial behaviour was to print a warning, but the warning triggers
at each boot and when the clock tree is refreshed.
This patch moves the print to debug and returns 0 instead of the
parent rate.
Fixes: 72dbb8c94d ("clk: meson: Add vid_pll divider driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190327151348.27402-1-narmstrong@baylibre.com
99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include "clk-regmap.h"
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#include "vid-pll-div.h"
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static inline struct meson_vid_pll_div_data *
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meson_vid_pll_div_data(struct clk_regmap *clk)
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{
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return (struct meson_vid_pll_div_data *)clk->data;
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}
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/*
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* This vid_pll divided is a fully programmable fractionnal divider to
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* achieve complex video clock rates.
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*
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* Here are provided the commonly used fraction values provided by Amlogic.
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*/
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struct vid_pll_div {
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unsigned int shift_val;
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unsigned int shift_sel;
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unsigned int divider;
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unsigned int multiplier;
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};
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#define VID_PLL_DIV(_val, _sel, _ft, _fb) \
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{ \
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.shift_val = (_val), \
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.shift_sel = (_sel), \
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.divider = (_ft), \
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.multiplier = (_fb), \
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}
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static const struct vid_pll_div vid_pll_div_table[] = {
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VID_PLL_DIV(0x0aaa, 0, 2, 1), /* 2/1 => /2 */
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VID_PLL_DIV(0x5294, 2, 5, 2), /* 5/2 => /2.5 */
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VID_PLL_DIV(0x0db6, 0, 3, 1), /* 3/1 => /3 */
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VID_PLL_DIV(0x36cc, 1, 7, 2), /* 7/2 => /3.5 */
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VID_PLL_DIV(0x6666, 2, 15, 4), /* 15/4 => /3.75 */
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VID_PLL_DIV(0x0ccc, 0, 4, 1), /* 4/1 => /4 */
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VID_PLL_DIV(0x739c, 2, 5, 1), /* 5/1 => /5 */
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VID_PLL_DIV(0x0e38, 0, 6, 1), /* 6/1 => /6 */
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VID_PLL_DIV(0x0000, 3, 25, 4), /* 25/4 => /6.25 */
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VID_PLL_DIV(0x3c78, 1, 7, 1), /* 7/1 => /7 */
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VID_PLL_DIV(0x78f0, 2, 15, 2), /* 15/2 => /7.5 */
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VID_PLL_DIV(0x0fc0, 0, 12, 1), /* 12/1 => /12 */
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VID_PLL_DIV(0x3f80, 1, 14, 1), /* 14/1 => /14 */
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VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */
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};
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#define to_meson_vid_pll_div(_hw) \
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container_of(_hw, struct meson_vid_pll_div, hw)
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static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
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unsigned int shift_sel)
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{
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int i;
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for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) {
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if (vid_pll_div_table[i].shift_val == shift_val &&
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vid_pll_div_table[i].shift_sel == shift_sel)
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return &vid_pll_div_table[i];
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}
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return NULL;
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}
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static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk);
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const struct vid_pll_div *div;
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div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
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meson_parm_read(clk->map, &pll_div->sel));
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if (!div || !div->divider) {
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pr_debug("%s: Invalid config value for vid_pll_div\n", __func__);
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return 0;
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}
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return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
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}
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const struct clk_ops meson_vid_pll_div_ro_ops = {
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.recalc_rate = meson_vid_pll_div_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(meson_vid_pll_div_ro_ops);
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MODULE_DESCRIPTION("Amlogic video pll divider driver");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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