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f450f11b2d
Get the updated header for the newly added VG register. Reviewed-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: James Clark <james.clark@arm.com> Cc: <broonie@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: German Gomez <german.gomez@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220525154114.718321-3-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
46 lines
1 KiB
C
46 lines
1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _ASM_ARM64_PERF_REGS_H
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#define _ASM_ARM64_PERF_REGS_H
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enum perf_event_arm_regs {
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PERF_REG_ARM64_X0,
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PERF_REG_ARM64_X1,
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PERF_REG_ARM64_X2,
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PERF_REG_ARM64_X3,
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PERF_REG_ARM64_X4,
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PERF_REG_ARM64_X5,
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PERF_REG_ARM64_X6,
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PERF_REG_ARM64_X7,
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PERF_REG_ARM64_X8,
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PERF_REG_ARM64_X9,
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PERF_REG_ARM64_X10,
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PERF_REG_ARM64_X11,
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PERF_REG_ARM64_X12,
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PERF_REG_ARM64_X13,
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PERF_REG_ARM64_X14,
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PERF_REG_ARM64_X15,
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PERF_REG_ARM64_X16,
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PERF_REG_ARM64_X17,
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PERF_REG_ARM64_X18,
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PERF_REG_ARM64_X19,
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PERF_REG_ARM64_X20,
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PERF_REG_ARM64_X21,
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PERF_REG_ARM64_X22,
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PERF_REG_ARM64_X23,
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PERF_REG_ARM64_X24,
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PERF_REG_ARM64_X25,
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PERF_REG_ARM64_X26,
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PERF_REG_ARM64_X27,
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PERF_REG_ARM64_X28,
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PERF_REG_ARM64_X29,
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PERF_REG_ARM64_LR,
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PERF_REG_ARM64_SP,
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PERF_REG_ARM64_PC,
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/* Extended/pseudo registers */
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PERF_REG_ARM64_VG = 46, // SVE Vector Granule
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PERF_REG_ARM64_MAX = PERF_REG_ARM64_PC + 1,
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PERF_REG_ARM64_EXTENDED_MAX = PERF_REG_ARM64_VG + 1
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};
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#endif /* _ASM_ARM64_PERF_REGS_H */
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