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147455edfe
Rename some variables from "jh7100" or "JH7100" to "jh71x0" or "JH71X0". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
123 lines
3.1 KiB
C
123 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __CLK_STARFIVE_JH71X0_H
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#define __CLK_STARFIVE_JH71X0_H
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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/* register fields */
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#define JH71X0_CLK_ENABLE BIT(31)
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#define JH71X0_CLK_INVERT BIT(30)
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#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
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#define JH71X0_CLK_MUX_SHIFT 24
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#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
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#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
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#define JH71X0_CLK_FRAC_SHIFT 8
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#define JH71X0_CLK_INT_MASK GENMASK(7, 0)
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/* fractional divider min/max */
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#define JH71X0_CLK_FRAC_MIN 100UL
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#define JH71X0_CLK_FRAC_MAX 25599UL
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/* clock data */
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struct jh71x0_clk_data {
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const char *name;
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unsigned long flags;
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u32 max;
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u8 parents[4];
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};
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#define JH71X0_GATE(_idx, _name, _flags, _parent) \
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[_idx] = { \
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.name = _name, \
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.flags = CLK_SET_RATE_PARENT | (_flags), \
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.max = JH71X0_CLK_ENABLE, \
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.parents = { [0] = _parent }, \
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}
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#define JH71X0__DIV(_idx, _name, _max, _parent) \
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[_idx] = { \
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.name = _name, \
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.flags = 0, \
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.max = _max, \
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.parents = { [0] = _parent }, \
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}
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#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
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[_idx] = { \
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.name = _name, \
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.flags = _flags, \
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.max = JH71X0_CLK_ENABLE | (_max), \
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.parents = { [0] = _parent }, \
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}
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#define JH71X0_FDIV(_idx, _name, _parent) \
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[_idx] = { \
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.name = _name, \
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.flags = 0, \
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.max = JH71X0_CLK_FRAC_MAX, \
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.parents = { [0] = _parent }, \
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}
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#define JH71X0__MUX(_idx, _name, _nparents, ...) \
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[_idx] = { \
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.name = _name, \
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.flags = 0, \
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.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
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.parents = { __VA_ARGS__ }, \
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}
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#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
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[_idx] = { \
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.name = _name, \
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.flags = _flags, \
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.max = JH71X0_CLK_ENABLE | \
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(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
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.parents = { __VA_ARGS__ }, \
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}
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#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
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[_idx] = { \
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.name = _name, \
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.flags = 0, \
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.max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
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.parents = { __VA_ARGS__ }, \
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}
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#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
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[_idx] = { \
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.name = _name, \
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.flags = _flags, \
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.max = JH71X0_CLK_ENABLE | \
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(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
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.parents = { __VA_ARGS__ }, \
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}
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#define JH71X0__INV(_idx, _name, _parent) \
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[_idx] = { \
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.name = _name, \
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.flags = CLK_SET_RATE_PARENT, \
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.max = JH71X0_CLK_INVERT, \
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.parents = { [0] = _parent }, \
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}
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struct jh71x0_clk {
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struct clk_hw hw;
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unsigned int idx;
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unsigned int max_div;
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};
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struct jh71x0_clk_priv {
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/* protect clk enable and set rate/parent from happening at the same time */
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spinlock_t rmw_lock;
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struct device *dev;
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void __iomem *base;
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struct clk_hw *pll[3];
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struct jh71x0_clk reg[];
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};
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const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
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#endif
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