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83f865d7e3
BCM6328 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
18 lines
476 B
C
18 lines
476 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __DT_BINDINGS_RESET_BCM6328_H
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#define __DT_BINDINGS_RESET_BCM6328_H
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#define BCM6328_RST_SPI 0
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#define BCM6328_RST_EPHY 1
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#define BCM6328_RST_SAR 2
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#define BCM6328_RST_ENETSW 3
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#define BCM6328_RST_USBS 4
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#define BCM6328_RST_USBH 5
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#define BCM6328_RST_PCM 6
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#define BCM6328_RST_PCIE_CORE 7
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#define BCM6328_RST_PCIE 8
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#define BCM6328_RST_PCIE_EXT 9
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#define BCM6328_RST_PCIE_HARD 10
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#endif /* __DT_BINDINGS_RESET_BCM6328_H */
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