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5ea61b478f
To support reset of infra_ao, add the index of infra_ao reset of thermal/svs for MT8186. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-18-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Runyang Chen <runyang.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8186
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/* TOPRGU resets */
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#define MT8186_TOPRGU_INFRA_SW_RST 0
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#define MT8186_TOPRGU_MM_SW_RST 1
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#define MT8186_TOPRGU_MFG_SW_RST 2
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#define MT8186_TOPRGU_VENC_SW_RST 3
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#define MT8186_TOPRGU_VDEC_SW_RST 4
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#define MT8186_TOPRGU_IMG_SW_RST 5
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#define MT8186_TOPRGU_DDR_SW_RST 6
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#define MT8186_TOPRGU_INFRA_AO_SW_RST 8
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#define MT8186_TOPRGU_CONNSYS_SW_RST 9
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#define MT8186_TOPRGU_APMIXED_SW_RST 10
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#define MT8186_TOPRGU_PWRAP_SW_RST 11
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#define MT8186_TOPRGU_CONN_MCU_SW_RST 12
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#define MT8186_TOPRGU_IPNNA_SW_RST 13
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#define MT8186_TOPRGU_WPE_SW_RST 14
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#define MT8186_TOPRGU_ADSP_SW_RST 15
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#define MT8186_TOPRGU_AUDIO_SW_RST 17
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#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18
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#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19
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#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20
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#define MT8186_TOPRGU_IPE_SW_RST 21
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#define MT8186_TOPRGU_IMG2_SW_RST 22
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#define MT8186_TOPRGU_SW_RST_NUM 23
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/* MMSYS resets */
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#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19
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/* INFRA resets */
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#define MT8186_INFRA_THERMAL_CTRL_RST 0
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#define MT8186_INFRA_PTP_CTRL_RST 1
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */
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