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2cf4ec5344
To support reset of infra_ao, add the index of infra_ao reset of thermal for MT8188. Signed-off-by: Runyang Chen <runyang.chen@mediatek.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230525075011.7032-2-runyang.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
41 lines
1.6 KiB
C
41 lines
1.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Runyang Chen <runyang.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8188
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#define MT8188_TOPRGU_CONN_MCU_SW_RST 0
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#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1
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#define MT8188_TOPRGU_IPU0_SW_RST 2
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#define MT8188_TOPRGU_IPU1_SW_RST 3
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#define MT8188_TOPRGU_IPU2_SW_RST 4
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#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5
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#define MT8188_TOPRGU_INFRA_SW_RST 6
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#define MT8188_TOPRGU_MMSYS_SW_RST 7
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#define MT8188_TOPRGU_MFG_SW_RST 8
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#define MT8188_TOPRGU_VENC_SW_RST 9
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#define MT8188_TOPRGU_VDEC_SW_RST 10
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#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11
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#define MT8188_TOPRGU_SCP_SW_RST 12
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#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13
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#define MT8188_TOPRGU_AUDIO_SW_RST 14
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#define MT8188_TOPRGU_CAMSYS_SW_RST 15
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#define MT8188_TOPRGU_MJC_SW_RST 16
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#define MT8188_TOPRGU_PERI_SW_RST 17
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#define MT8188_TOPRGU_PERI_AO_SW_RST 18
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#define MT8188_TOPRGU_PCIE_SW_RST 19
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#define MT8188_TOPRGU_ADSPSYS_SW_RST 21
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#define MT8188_TOPRGU_DPTX_SW_RST 22
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#define MT8188_TOPRGU_SPMI_MST_SW_RST 23
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#define MT8188_TOPRGU_SW_RST_NUM 24
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/* INFRA resets */
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#define MT8188_INFRA_RST1_THERMAL_MCU_RST 0
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#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1
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#define MT8188_INFRA_RST3_PTP_CTRL_RST 2
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
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