mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 05:44:11 +00:00
fb91526b5f
To support reset of infra_ao, add the index of infra_ao reset of thermal/svs/pcei for MT8192 and thermal/svs for MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-14-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2020 MediaTek Inc.
|
|
* Author: Yong Liang <yong.liang@mediatek.com>
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
|
|
#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
|
|
|
|
/* TOPRGU resets */
|
|
#define MT8192_TOPRGU_MM_SW_RST 1
|
|
#define MT8192_TOPRGU_MFG_SW_RST 2
|
|
#define MT8192_TOPRGU_VENC_SW_RST 3
|
|
#define MT8192_TOPRGU_VDEC_SW_RST 4
|
|
#define MT8192_TOPRGU_IMG_SW_RST 5
|
|
#define MT8192_TOPRGU_MD_SW_RST 7
|
|
#define MT8192_TOPRGU_CONN_SW_RST 9
|
|
#define MT8192_TOPRGU_CONN_MCU_SW_RST 12
|
|
#define MT8192_TOPRGU_IPU0_SW_RST 14
|
|
#define MT8192_TOPRGU_IPU1_SW_RST 15
|
|
#define MT8192_TOPRGU_AUDIO_SW_RST 17
|
|
#define MT8192_TOPRGU_CAMSYS_SW_RST 18
|
|
#define MT8192_TOPRGU_MJC_SW_RST 19
|
|
#define MT8192_TOPRGU_C2K_S2_SW_RST 20
|
|
#define MT8192_TOPRGU_C2K_SW_RST 21
|
|
#define MT8192_TOPRGU_PERI_SW_RST 22
|
|
#define MT8192_TOPRGU_PERI_AO_SW_RST 23
|
|
|
|
#define MT8192_TOPRGU_SW_RST_NUM 23
|
|
|
|
/* MMSYS resets */
|
|
#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
|
|
|
|
/* INFRA resets */
|
|
#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0
|
|
#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1
|
|
#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2
|
|
#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3
|
|
#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4
|
|
|
|
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
|