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c9f4c6cf53
smc allocates a certain number of CQ entries for used RoCE devices. For mlx5 devices the chosen constant number results in a large allocation causing this warning: [13355.124656] WARNING: CPU: 3 PID: 16535 at mm/page_alloc.c:3883 __alloc_pages_nodemask+0x2be/0x10c0 [13355.124657] Modules linked in: smc_diag(O) smc(O) xt_CHECKSUM iptable_mangle ipt_MASQUERADE nf_nat_masquerade_ipv4 iptable_nat nf_nat_ipv4 nf_nat nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack ipt_REJECT nf_reject_ipv4 xt_tcpudp bridge stp llc ip6table_filter ip6_tables iptable_filter mlx5_ib ib_core sunrpc mlx5_core s390_trng rng_core ghash_s390 prng aes_s390 des_s390 des_generic sha512_s390 sha256_s390 sha1_s390 sha_common ptp pps_core eadm_sch dm_multipath dm_mod vhost_net tun vhost tap sch_fq_codel kvm ip_tables x_tables autofs4 [last unloaded: smc] [13355.124672] CPU: 3 PID: 16535 Comm: kworker/3:0 Tainted: G O 4.14.0uschi #1 [13355.124673] Hardware name: IBM 3906 M04 704 (LPAR) [13355.124675] Workqueue: events smc_listen_work [smc] [13355.124677] task: 00000000e2f22100 task.stack: 0000000084720000 [13355.124678] Krnl PSW : 0704c00180000000 000000000029da76 (__alloc_pages_nodemask+0x2be/0x10c0) [13355.124681] R:0 T:1 IO:1 EX:1 Key:0 M:1 W:0 P:0 AS:3 CC:0 PM:0 RI:0 EA:3 [13355.124682] Krnl GPRS: 0000000000000000 00550e00014080c0 0000000000000000 0000000000000001 [13355.124684] 000000000029d8b6 00000000f3bfd710 0000000000000000 00000000014080c0 [13355.124685] 0000000000000009 00000000ec277a00 0000000000200000 0000000000000000 [13355.124686] 0000000000000000 00000000000001ff 000000000029d8b6 0000000084723720 [13355.124708] Krnl Code: 000000000029da6a: a7110200 tmll %r1,512 000000000029da6e: a774ff29 brc 7,29d8c0 #000000000029da72: a7f40001 brc 15,29da74 >000000000029da76: a7f4ff25 brc 15,29d8c0 000000000029da7a: a7380000 lhi %r3,0 000000000029da7e: a7f4fef1 brc 15,29d860 000000000029da82: 5820f0c4 l %r2,196(%r15) 000000000029da86: a53e0048 llilh %r3,72 [13355.124720] Call Trace: [13355.124722] ([<000000000029d8b6>] __alloc_pages_nodemask+0xfe/0x10c0) [13355.124724] [<000000000013bd1e>] s390_dma_alloc+0x6e/0x148 [13355.124733] [<000003ff802eeba6>] mlx5_dma_zalloc_coherent_node+0x8e/0xe0 [mlx5_core] [13355.124740] [<000003ff802eee18>] mlx5_buf_alloc_node+0x70/0x108 [mlx5_core] [13355.124744] [<000003ff804eb410>] mlx5_ib_create_cq+0x558/0x898 [mlx5_ib] [13355.124749] [<000003ff80407d40>] ib_create_cq+0x48/0x88 [ib_core] [13355.124751] [<000003ff80109fba>] smc_ib_setup_per_ibdev+0x52/0x118 [smc] [13355.124753] [<000003ff8010bcb6>] smc_conn_create+0x65e/0x728 [smc] [13355.124755] [<000003ff801081a2>] smc_listen_work+0x2d2/0x540 [smc] [13355.124756] [<0000000000162c66>] process_one_work+0x1be/0x440 [13355.124758] [<0000000000162f40>] worker_thread+0x58/0x458 [13355.124759] [<0000000000169e7e>] kthread+0x14e/0x168 [13355.124760] [<00000000009ce8be>] kernel_thread_starter+0x6/0xc [13355.124762] [<00000000009ce8b8>] kernel_thread_starter+0x0/0xc [13355.124762] Last Breaking-Event-Address: [13355.124764] [<000000000029da72>] __alloc_pages_nodemask+0x2ba/0x10c0 [13355.124764] ---[ end trace 34be38b581c0b585 ]--- This patch reduces the smc constant for the maximum number of allocated completion queue entries SMC_MAX_CQE by 2 to avoid high round up values in the mlx5 code, and reduces the number of allocated completion queue entries even more, if the final allocation for an mlx5 device hits the MAX_ORDER limit. Reported-by: Ihnken Menssen <menssen@de.ibm.com> Signed-off-by: Ursula Braun <ubraun@linux.vnet.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Shared Memory Communications over RDMA (SMC-R) and RoCE
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*
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* Work Requests exploiting Infiniband API
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*
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* Copyright IBM Corp. 2016
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*
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* Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
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*/
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#ifndef SMC_WR_H
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#define SMC_WR_H
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#include <linux/atomic.h>
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#include <rdma/ib_verbs.h>
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#include <asm/div64.h>
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#include "smc.h"
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#include "smc_core.h"
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#define SMC_WR_BUF_CNT 16 /* # of ctrl buffers per link */
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#define SMC_WR_TX_WAIT_FREE_SLOT_TIME (10 * HZ)
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#define SMC_WR_TX_WAIT_PENDING_TIME (5 * HZ)
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#define SMC_WR_TX_SIZE 44 /* actual size of wr_send data (<=SMC_WR_BUF_SIZE) */
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#define SMC_WR_TX_PEND_PRIV_SIZE 32
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struct smc_wr_tx_pend_priv {
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u8 priv[SMC_WR_TX_PEND_PRIV_SIZE];
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};
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typedef void (*smc_wr_tx_handler)(struct smc_wr_tx_pend_priv *,
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struct smc_link *,
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enum ib_wc_status);
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typedef bool (*smc_wr_tx_filter)(struct smc_wr_tx_pend_priv *,
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unsigned long);
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typedef void (*smc_wr_tx_dismisser)(struct smc_wr_tx_pend_priv *);
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struct smc_wr_rx_handler {
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struct hlist_node list; /* hash table collision resolution */
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void (*handler)(struct ib_wc *, void *);
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u8 type;
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};
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/* Only used by RDMA write WRs.
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* All other WRs (CDC/LLC) use smc_wr_tx_send handling WR_ID implicitly
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*/
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static inline long smc_wr_tx_get_next_wr_id(struct smc_link *link)
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{
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return atomic_long_inc_return(&link->wr_tx_id);
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}
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static inline void smc_wr_tx_set_wr_id(atomic_long_t *wr_tx_id, long val)
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{
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atomic_long_set(wr_tx_id, val);
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}
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/* post a new receive work request to fill a completed old work request entry */
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static inline int smc_wr_rx_post(struct smc_link *link)
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{
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struct ib_recv_wr *bad_recv_wr = NULL;
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int rc;
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u64 wr_id, temp_wr_id;
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u32 index;
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wr_id = ++link->wr_rx_id; /* tasklet context, thus not atomic */
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temp_wr_id = wr_id;
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index = do_div(temp_wr_id, link->wr_rx_cnt);
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link->wr_rx_ibs[index].wr_id = wr_id;
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rc = ib_post_recv(link->roce_qp, &link->wr_rx_ibs[index], &bad_recv_wr);
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return rc;
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}
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int smc_wr_create_link(struct smc_link *lnk);
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int smc_wr_alloc_link_mem(struct smc_link *lnk);
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void smc_wr_free_link(struct smc_link *lnk);
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void smc_wr_free_link_mem(struct smc_link *lnk);
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void smc_wr_remember_qp_attr(struct smc_link *lnk);
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void smc_wr_remove_dev(struct smc_ib_device *smcibdev);
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void smc_wr_add_dev(struct smc_ib_device *smcibdev);
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int smc_wr_tx_get_free_slot(struct smc_link *link, smc_wr_tx_handler handler,
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struct smc_wr_buf **wr_buf,
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struct smc_wr_tx_pend_priv **wr_pend_priv);
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int smc_wr_tx_put_slot(struct smc_link *link,
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struct smc_wr_tx_pend_priv *wr_pend_priv);
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int smc_wr_tx_send(struct smc_link *link,
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struct smc_wr_tx_pend_priv *wr_pend_priv);
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void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context);
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void smc_wr_tx_dismiss_slots(struct smc_link *lnk, u8 wr_rx_hdr_type,
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smc_wr_tx_filter filter,
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smc_wr_tx_dismisser dismisser,
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unsigned long data);
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int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler);
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int smc_wr_rx_post_init(struct smc_link *link);
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void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context);
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int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr);
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#endif /* SMC_WR_H */
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