Remi Pommarel af3f5722d1 phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver ... This adds support for the MIPI analog PHY which is also used for PCIE found in the Amlogic AXG SoC Family. MIPI or PCIE selection is done by the #phy-cells, making the mode static and exclusive. For now only PCIE functionality is supported. This PHY will be used to replace the mipi_enable clock gating logic which was mistakenly added in the clock subsystem. This also activates a non documented band gap bit in those registers that allows reliable PCIE clock signal generation on AXG platforms. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com>		2020-03-04 10:53:30 +00:00
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Kconfig	phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver	2020-03-04 10:53:30 +00:00
Makefile	phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver	2020-03-04 10:53:30 +00:00
phy-meson-axg-mipi-pcie-analog.c	phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver	2020-03-04 10:53:30 +00:00
phy-meson-g12a-usb2.c	phy: amlogic: add Amlogic G12A USB2 PHY Driver	2019-04-17 14:12:50 +05:30
phy-meson-g12a-usb3-pcie.c	phy: meson-g12a-usb3-pcie: Add support for PCIe mode	2019-10-15 14:57:32 +01:00
phy-meson-gxl-usb2.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446	2019-06-05 17:37:18 +02:00
phy-meson-gxl-usb3.c	phy: core: rework phy_set_mode to accept phy mode and submode	2018-12-12 10:01:33 +05:30
phy-meson8b-usb2.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446	2019-06-05 17:37:18 +02:00