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af6a50d457
i.MX6ULL has errata ERR010450, point out that due to SOC I/O timing limitation, for eMMC HS200 and SD/SDIO 3.0 SDR104, the clock rate can't exceed 150MHz. And for eMMC DDR52 and SD/SDIO DDR50 mode, the clock rate can't exceed 45MHz. This patch add this limit for imx6ull. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> [Ulf: Fixed comments and whitespace] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
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