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b633648c5a
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#include <asm/irqflags.h>
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#include <asm/hazards.h>
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#include <linux/compiler.h>
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#include <linux/preempt.h>
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#include <linux/export.h>
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#include <linux/stringify.h>
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#ifndef CONFIG_CPU_MIPSR2
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/*
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* For cli() we have to insert nops to make sure that the new value
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* has actually arrived in the status register before the end of this
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* macro.
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* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
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* no nops at all.
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*/
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/*
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* For TX49, operating only IE bit is not enough.
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*
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* If mfc0 $12 follows store and the mfc0 is last instruction of a
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* page and fetching the next instruction causes TLB miss, the result
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* of the mfc0 might wrongly contain EXL bit.
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*
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* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
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*
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* Workaround: mask EXL bit of the result or place a nop before mfc0.
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*/
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notrace void arch_local_irq_disable(void)
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{
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preempt_disable();
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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#if defined(CONFIG_CPU_MIPSR2)
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/* see irqflags.h for inline function */
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#else
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" mfc0 $1,$12 \n"
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" ori $1,0x1f \n"
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" xori $1,0x1f \n"
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" .set noreorder \n"
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" mtc0 $1,$12 \n"
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#endif
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" " __stringify(__irq_disable_hazard) " \n"
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" .set pop \n"
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: /* no outputs */
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: /* no inputs */
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: "memory");
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preempt_enable();
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}
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EXPORT_SYMBOL(arch_local_irq_disable);
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notrace unsigned long arch_local_irq_save(void)
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{
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unsigned long flags;
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preempt_disable();
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__asm__ __volatile__(
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" .set push \n"
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" .set reorder \n"
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" .set noat \n"
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#if defined(CONFIG_CPU_MIPSR2)
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/* see irqflags.h for inline function */
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#else
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" mfc0 %[flags], $12 \n"
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" ori $1, %[flags], 0x1f \n"
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" xori $1, 0x1f \n"
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" .set noreorder \n"
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" mtc0 $1, $12 \n"
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#endif
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" " __stringify(__irq_disable_hazard) " \n"
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" .set pop \n"
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: [flags] "=r" (flags)
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: /* no inputs */
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: "memory");
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preempt_enable();
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return flags;
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}
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EXPORT_SYMBOL(arch_local_irq_save);
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notrace void arch_local_irq_restore(unsigned long flags)
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{
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unsigned long __tmp1;
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preempt_disable();
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
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/* see irqflags.h for inline function */
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#elif defined(CONFIG_CPU_MIPSR2)
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/* see irqflags.h for inline function */
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#else
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" mfc0 $1, $12 \n"
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" andi %[flags], 1 \n"
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" ori $1, 0x1f \n"
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" xori $1, 0x1f \n"
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" or %[flags], $1 \n"
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" mtc0 %[flags], $12 \n"
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#endif
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" " __stringify(__irq_disable_hazard) " \n"
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" .set pop \n"
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: [flags] "=r" (__tmp1)
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: "0" (flags)
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: "memory");
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preempt_enable();
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}
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EXPORT_SYMBOL(arch_local_irq_restore);
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notrace void __arch_local_irq_restore(unsigned long flags)
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{
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unsigned long __tmp1;
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preempt_disable();
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
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/* see irqflags.h for inline function */
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#elif defined(CONFIG_CPU_MIPSR2)
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/* see irqflags.h for inline function */
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#else
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" mfc0 $1, $12 \n"
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" andi %[flags], 1 \n"
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" ori $1, 0x1f \n"
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" xori $1, 0x1f \n"
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" or %[flags], $1 \n"
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" mtc0 %[flags], $12 \n"
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#endif
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" " __stringify(__irq_disable_hazard) " \n"
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" .set pop \n"
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: [flags] "=r" (__tmp1)
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: "0" (flags)
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: "memory");
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preempt_enable();
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}
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EXPORT_SYMBOL(__arch_local_irq_restore);
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#endif /* !CONFIG_CPU_MIPSR2 */
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