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Ensure all platform specific event flags are within PERF_EVENT_FLAG_ARCH. Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: James Clark <james.clark@arm.com> Link: https://lkml.kernel.org/r/20220907091924.439193-5-anshuman.khandual@arm.com
22 lines
1.1 KiB
C
22 lines
1.1 KiB
C
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/*
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* struct hw_perf_event.flags flags
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*/
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PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
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PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
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PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
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PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
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PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
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PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
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PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
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/* 0x00080 */
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PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
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PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
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PERF_ARCH(LARGE_PEBS, 0x00400) /* use large PEBS */
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PERF_ARCH(PEBS_VIA_PT, 0x00800) /* use PT buffer for PEBS */
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PERF_ARCH(PAIR, 0x01000) /* Large Increment per Cycle */
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PERF_ARCH(LBR_SELECT, 0x02000) /* Save/Restore MSR_LBR_SELECT */
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PERF_ARCH(TOPDOWN, 0x04000) /* Count Topdown slots/metrics events */
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PERF_ARCH(PEBS_STLAT, 0x08000) /* st+stlat data address sampling */
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PERF_ARCH(AMD_BRS, 0x10000) /* AMD Branch Sampling */
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PERF_ARCH(PEBS_LAT_HYBRID, 0x20000) /* ld and st lat for hybrid */
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