Yicong Yang dc01bfdc3d perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09 ... [ Upstream commit 0242737dc4 ] Some HiSilicon SMMU PMCG suffers the erratum 162001900 that the PMU disable control sometimes fail to disable the counters. This will lead to error or inaccurate data since before we enable the counters the counter's still counting for the event used in last perf session. This patch tries to fix this by hardening the global disable process. Before disable the PMU, writing an invalid event type (0xffff) to focibly stop the counters. Correspondingly restore each events on pmu::pmu_enable(). Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20230814124012.58013-1-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2023-09-23 11:01:05 +02:00
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acpi_object_usage.rst
amu.rst	Documentation: Chinese translation of Documentation/arm64/amu.rst	2020-09-28 15:24:24 -06:00
arm-acpi.rst
booting.rst
cpu-feature-registers.rst	arm64: cpufeature: add HWCAP for FEAT_RPRES	2022-03-11 12:11:51 +01:00
elf_hwcaps.rst	arm64: cpufeature: add HWCAP for FEAT_RPRES	2022-03-11 12:11:51 +01:00
hugetlbpage.rst	Documentation: Chinese translation of Documentation/arm64/hugetlbpage.rst	2020-10-21 15:15:17 -06:00
index.rst	As hoped, things calmed down for docs this cycle; fewer changes and almost	2020-10-12 16:21:29 -07:00
kasan-offsets.sh
legacy_instructions.rst
memory-tagging-extension.rst	arm64: mte: Document that user PSTATE.TCO is ignored by kernel uaccess	2020-10-28 17:50:39 +00:00
memory.rst
perf.rst
pointer-authentication.rst
silicon-errata.rst	perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09	2023-09-23 11:01:05 +02:00
sve.rst
tagged-address-abi.rst	userfaultfd: do not untag user pointers	2021-07-28 14:35:46 +02:00
tagged-pointers.rst