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c78a41fc04
As a final bit of preparation for converting to ARCH_MULTIPLATFORM, change the interrupt handling for s3c24xx to use sparse IRQs. Since the number of possible interrupts is already fixed and relatively small per chip, just make it use all legacy interrupts preallocated using the .nr_irqs field in the machine descriptor, rather than actually allocating domains on the fly. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
100 lines
2.2 KiB
C
100 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2008-2009 Samsung Electronics
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/fb.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <video/platform_lcd.h>
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#include <video/samsung_fimd.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include "irqs.h"
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#include "map.h"
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <linux/platform_data/i2c-s3c2410.h>
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#include "fb.h"
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#include "devs.h"
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#include "cpu.h"
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#include "s3c64xx.h"
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#define UCON S3C2410_UCON_DEFAULT
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
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/* REVISIT: NCP uses only serial 1, 2 */
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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};
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static struct platform_device *ncp_devices[] __initdata = {
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&s3c_device_hsmmc1,
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&s3c_device_i2c0,
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};
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static struct map_desc ncp_iodesc[] __initdata = {};
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static void __init ncp_map_io(void)
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{
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s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
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s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
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}
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static void __init ncp_machine_init(void)
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{
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s3c_i2c0_set_platdata(NULL);
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platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
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}
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MACHINE_START(NCP, "NCP")
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/* Maintainer: Samsung Electronics */
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.atag_offset = 0x100,
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.nr_irqs = S3C64XX_NR_IRQS,
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.init_irq = s3c6410_init_irq,
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.map_io = ncp_map_io,
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.init_machine = ncp_machine_init,
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.init_time = s3c64xx_timer_init,
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MACHINE_END
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