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![Greg Kroah-Hartman](/assets/img/avatar_default.png)
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
463 lines
12 KiB
C
463 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Cortina Gemini SoC Clock Controller driver
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* Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
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*/
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#define pr_fmt(fmt) "clk-gemini: " fmt
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/reset/cortina,gemini-reset.h>
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#include <dt-bindings/clock/cortina,gemini-clock.h>
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/* Globally visible clocks */
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static DEFINE_SPINLOCK(gemini_clk_lock);
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#define GEMINI_GLOBAL_STATUS 0x04
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#define PLL_OSC_SEL BIT(30)
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#define AHBSPEED_SHIFT (15)
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#define AHBSPEED_MASK 0x07
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#define CPU_AHB_RATIO_SHIFT (18)
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#define CPU_AHB_RATIO_MASK 0x03
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#define GEMINI_GLOBAL_PLL_CONTROL 0x08
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#define GEMINI_GLOBAL_SOFT_RESET 0x0c
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#define GEMINI_GLOBAL_MISC_CONTROL 0x30
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#define PCI_CLK_66MHZ BIT(18)
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#define GEMINI_GLOBAL_CLOCK_CONTROL 0x34
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#define PCI_CLKRUN_EN BIT(16)
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#define TVC_HALFDIV_SHIFT (24)
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#define TVC_HALFDIV_MASK 0x1f
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#define SECURITY_CLK_SEL BIT(29)
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#define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44
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#define PCI_DLL_BYPASS BIT(31)
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#define PCI_DLL_TAP_SEL_MASK 0x1f
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/**
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* struct gemini_data_data - Gemini gated clocks
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* @bit_idx: the bit used to gate this clock in the clock register
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* @name: the clock name
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* @parent_name: the name of the parent clock
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* @flags: standard clock framework flags
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*/
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struct gemini_gate_data {
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u8 bit_idx;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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};
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/**
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* struct clk_gemini_pci - Gemini PCI clock
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* @hw: corresponding clock hardware entry
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* @map: regmap to access the registers
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* @rate: current rate
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*/
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struct clk_gemini_pci {
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struct clk_hw hw;
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struct regmap *map;
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unsigned long rate;
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};
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/**
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* struct gemini_reset - gemini reset controller
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* @map: regmap to access the containing system controller
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* @rcdev: reset controller device
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*/
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struct gemini_reset {
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struct regmap *map;
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struct reset_controller_dev rcdev;
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};
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/* Keeps track of all clocks */
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static struct clk_hw_onecell_data *gemini_clk_data;
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static const struct gemini_gate_data gemini_gates[] = {
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{ 1, "security-gate", "secdiv", 0 },
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{ 2, "gmac0-gate", "ahb", 0 },
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{ 3, "gmac1-gate", "ahb", 0 },
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{ 4, "sata0-gate", "ahb", 0 },
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{ 5, "sata1-gate", "ahb", 0 },
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{ 6, "usb0-gate", "ahb", 0 },
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{ 7, "usb1-gate", "ahb", 0 },
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{ 8, "ide-gate", "ahb", 0 },
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{ 9, "pci-gate", "ahb", 0 },
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/*
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* The DDR controller may never have a driver, but certainly must
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* not be gated off.
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*/
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{ 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
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/*
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* The flash controller must be on to access NOR flash through the
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* memory map.
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*/
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{ 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
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{ 12, "tvc-gate", "ahb", 0 },
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{ 13, "boot-gate", "apb", 0 },
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};
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#define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
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#define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
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static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_gemini_pci *pciclk = to_pciclk(hw);
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u32 val;
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regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
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if (val & PCI_CLK_66MHZ)
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return 66000000;
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return 33000000;
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}
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static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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/* We support 33 and 66 MHz */
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if (rate < 48000000)
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return 33000000;
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return 66000000;
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}
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static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_gemini_pci *pciclk = to_pciclk(hw);
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if (rate == 33000000)
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return regmap_update_bits(pciclk->map,
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GEMINI_GLOBAL_MISC_CONTROL,
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PCI_CLK_66MHZ, 0);
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if (rate == 66000000)
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return regmap_update_bits(pciclk->map,
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GEMINI_GLOBAL_MISC_CONTROL,
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0, PCI_CLK_66MHZ);
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return -EINVAL;
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}
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static int gemini_pci_enable(struct clk_hw *hw)
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{
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struct clk_gemini_pci *pciclk = to_pciclk(hw);
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regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
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0, PCI_CLKRUN_EN);
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return 0;
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}
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static void gemini_pci_disable(struct clk_hw *hw)
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{
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struct clk_gemini_pci *pciclk = to_pciclk(hw);
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regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
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PCI_CLKRUN_EN, 0);
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}
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static int gemini_pci_is_enabled(struct clk_hw *hw)
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{
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struct clk_gemini_pci *pciclk = to_pciclk(hw);
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unsigned int val;
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regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
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return !!(val & PCI_CLKRUN_EN);
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}
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static const struct clk_ops gemini_pci_clk_ops = {
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.recalc_rate = gemini_pci_recalc_rate,
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.round_rate = gemini_pci_round_rate,
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.set_rate = gemini_pci_set_rate,
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.enable = gemini_pci_enable,
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.disable = gemini_pci_disable,
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.is_enabled = gemini_pci_is_enabled,
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};
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static struct clk_hw *gemini_pci_clk_setup(const char *name,
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const char *parent_name,
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struct regmap *map)
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{
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struct clk_gemini_pci *pciclk;
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struct clk_init_data init;
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int ret;
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pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
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if (!pciclk)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &gemini_pci_clk_ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pciclk->map = map;
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pciclk->hw.init = &init;
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ret = clk_hw_register(NULL, &pciclk->hw);
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if (ret) {
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kfree(pciclk);
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return ERR_PTR(ret);
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}
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return &pciclk->hw;
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}
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/*
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* This is a self-deasserting reset controller.
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*/
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static int gemini_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct gemini_reset *gr = to_gemini_reset(rcdev);
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/* Manual says to always set BIT 30 (CPU1) to 1 */
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return regmap_write(gr->map,
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GEMINI_GLOBAL_SOFT_RESET,
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BIT(GEMINI_RESET_CPU1) | BIT(id));
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}
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static int gemini_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return 0;
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}
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static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return 0;
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}
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static int gemini_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct gemini_reset *gr = to_gemini_reset(rcdev);
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u32 val;
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int ret;
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ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
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if (ret)
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return ret;
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return !!(val & BIT(id));
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}
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static const struct reset_control_ops gemini_reset_ops = {
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.reset = gemini_reset,
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.assert = gemini_reset_assert,
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.deassert = gemini_reset_deassert,
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.status = gemini_reset_status,
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};
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static int gemini_clk_probe(struct platform_device *pdev)
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{
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/* Gives the fracions 1x, 1.5x, 1.85x and 2x */
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unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
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unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
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void __iomem *base;
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struct gemini_reset *gr;
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struct regmap *map;
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struct clk_hw *hw;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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unsigned int mult, div;
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struct resource *res;
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u32 val;
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int ret;
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int i;
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gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
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if (!gr)
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return -ENOMEM;
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/* Remap the system controller for the exclusive register */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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map = syscon_node_to_regmap(np);
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if (IS_ERR(map)) {
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dev_err(dev, "no syscon regmap\n");
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return PTR_ERR(map);
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}
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gr->map = map;
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gr->rcdev.owner = THIS_MODULE;
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gr->rcdev.nr_resets = 32;
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gr->rcdev.ops = &gemini_reset_ops;
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gr->rcdev.of_node = np;
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ret = devm_reset_controller_register(dev, &gr->rcdev);
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if (ret) {
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dev_err(dev, "could not register reset controller\n");
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return ret;
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}
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/* RTC clock 32768 Hz */
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hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
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gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
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/* CPU clock derived as a fixed ratio from the AHB clock */
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regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
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val >>= CPU_AHB_RATIO_SHIFT;
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val &= CPU_AHB_RATIO_MASK;
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hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
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cpu_ahb_mult[val],
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cpu_ahb_div[val]);
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gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
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/* Security clock is 1:1 or 0.75 of APB */
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regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
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if (val & SECURITY_CLK_SEL) {
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mult = 1;
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div = 1;
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} else {
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mult = 3;
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div = 4;
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}
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hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
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/*
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* These are the leaf gates, at boot no clocks are gated.
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*/
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for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
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const struct gemini_gate_data *gd;
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gd = &gemini_gates[i];
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gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
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clk_hw_register_gate(NULL, gd->name,
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gd->parent_name,
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gd->flags,
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base + GEMINI_GLOBAL_CLOCK_CONTROL,
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gd->bit_idx,
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CLK_GATE_SET_TO_DISABLE,
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&gemini_clk_lock);
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}
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/*
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* The TV Interface Controller has a 5-bit half divider register.
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* This clock is supposed to be 27MHz as this is an exact multiple
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* of PAL and NTSC frequencies. The register is undocumented :(
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* FIXME: figure out the parent and how the divider works.
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*/
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mult = 1;
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div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
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dev_dbg(dev, "TVC half divider value = %d\n", div);
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div += 1;
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hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
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gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
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/* FIXME: very unclear what the parent is */
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hw = gemini_pci_clk_setup("PCI", "xtal", map);
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gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
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/* FIXME: very unclear what the parent is */
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hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
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gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
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return 0;
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}
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static const struct of_device_id gemini_clk_dt_ids[] = {
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{ .compatible = "cortina,gemini-syscon", },
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{ /* sentinel */ },
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};
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static struct platform_driver gemini_clk_driver = {
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.probe = gemini_clk_probe,
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.driver = {
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.name = "gemini-clk",
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.of_match_table = gemini_clk_dt_ids,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(gemini_clk_driver);
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static void __init gemini_cc_init(struct device_node *np)
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{
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struct regmap *map;
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struct clk_hw *hw;
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unsigned long freq;
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unsigned int mult, div;
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u32 val;
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int ret;
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int i;
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gemini_clk_data = kzalloc(sizeof(*gemini_clk_data) +
|
|
sizeof(*gemini_clk_data->hws) * GEMINI_NUM_CLKS,
|
|
GFP_KERNEL);
|
|
if (!gemini_clk_data)
|
|
return;
|
|
|
|
/*
|
|
* This way all clock fetched before the platform device probes,
|
|
* except those we assign here for early use, will be deferred.
|
|
*/
|
|
for (i = 0; i < GEMINI_NUM_CLKS; i++)
|
|
gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
|
|
|
|
map = syscon_node_to_regmap(np);
|
|
if (IS_ERR(map)) {
|
|
pr_err("no syscon regmap\n");
|
|
return;
|
|
}
|
|
/*
|
|
* We check that the regmap works on this very first access,
|
|
* but as this is an MMIO-backed regmap, subsequent regmap
|
|
* access is not going to fail and we skip error checks from
|
|
* this point.
|
|
*/
|
|
ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
|
|
if (ret) {
|
|
pr_err("failed to read global status register\n");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* XTAL is the crystal oscillator, 60 or 30 MHz selected from
|
|
* strap pin E6
|
|
*/
|
|
if (val & PLL_OSC_SEL)
|
|
freq = 30000000;
|
|
else
|
|
freq = 60000000;
|
|
hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
|
|
pr_debug("main crystal @%lu MHz\n", freq / 1000000);
|
|
|
|
/* VCO clock derived from the crystal */
|
|
mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
|
|
div = 2;
|
|
/* If we run on 30 MHz crystal we have to multiply with two */
|
|
if (val & PLL_OSC_SEL)
|
|
mult *= 2;
|
|
hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
|
|
|
|
/* The AHB clock is always 1/3 of the VCO */
|
|
hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
|
|
gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
|
|
|
|
/* The APB clock is always 1/6 of the AHB */
|
|
hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
|
|
gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
|
|
|
|
/* Register the clocks to be accessed by the device tree */
|
|
gemini_clk_data->num = GEMINI_NUM_CLKS;
|
|
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
|
|
}
|
|
CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
|