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39785eb1d3
The Freescale DIU framebuffer driver defines two constants, MIN_PIX_CLK and MAX_PIX_CLK, that are supposed to represent the lower and upper limits of the pixel clock. These values, however, are true only for one platform clock rate (533MHz) and only for the MPC8610. So the actual range for the pixel clock is chip-specific, which means the current values are almost always wrong. The chance of an out-of-range pixel clock being used are also remote. Rather than try to detect an out-of-range clock in the DIU driver, we depend on the board-specific pixel clock function (e.g. p1022ds_set_pixel_clock) to clamp the pixel clock to a supported value. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
216 lines
5 KiB
C
216 lines
5 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* Freescale DIU Frame Buffer device driver
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*
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* Authors: Hongjun Chen <hong-jun.chen@freescale.com>
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* Paul Widmer <paul.widmer@freescale.com>
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* Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* York Sun <yorksun@freescale.com>
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*
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* Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __FSL_DIU_FB_H__
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#define __FSL_DIU_FB_H__
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/* Arbitrary threshold to determine the allocation method
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* See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
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*/
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#define MEM_ALLOC_THRESHOLD (1024*768*4+32)
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#include <linux/types.h>
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struct mfb_alpha {
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int enable;
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int alpha;
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};
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struct mfb_chroma_key {
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int enable;
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__u8 red_max;
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__u8 green_max;
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__u8 blue_max;
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__u8 red_min;
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__u8 green_min;
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__u8 blue_min;
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};
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struct aoi_display_offset {
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int x_aoi_d;
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int y_aoi_d;
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};
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#define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
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#define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
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#define MFB_SET_ALPHA 0x80014d00
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#define MFB_GET_ALPHA 0x40014d00
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#define MFB_SET_AOID 0x80084d04
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#define MFB_GET_AOID 0x40084d04
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#define MFB_SET_PIXFMT 0x80014d08
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#define MFB_GET_PIXFMT 0x40014d08
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#define FBIOGET_GWINFO 0x46E0
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#define FBIOPUT_GWINFO 0x46E1
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#ifdef __KERNEL__
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#include <linux/spinlock.h>
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/*
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* These are the fields of area descriptor(in DDR memory) for every plane
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*/
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struct diu_ad {
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/* Word 0(32-bit) in DDR memory */
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/* __u16 comp; */
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/* __u16 pixel_s:2; */
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/* __u16 pallete:1; */
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/* __u16 red_c:2; */
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/* __u16 green_c:2; */
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/* __u16 blue_c:2; */
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/* __u16 alpha_c:3; */
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/* __u16 byte_f:1; */
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/* __u16 res0:3; */
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__be32 pix_fmt; /* hard coding pixel format */
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/* Word 1(32-bit) in DDR memory */
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__le32 addr;
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/* Word 2(32-bit) in DDR memory */
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/* __u32 delta_xs:11; */
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/* __u32 res1:1; */
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/* __u32 delta_ys:11; */
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/* __u32 res2:1; */
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/* __u32 g_alpha:8; */
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__le32 src_size_g_alpha;
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/* Word 3(32-bit) in DDR memory */
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/* __u32 delta_xi:11; */
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/* __u32 res3:5; */
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/* __u32 delta_yi:11; */
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/* __u32 res4:3; */
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/* __u32 flip:2; */
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__le32 aoi_size;
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/* Word 4(32-bit) in DDR memory */
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/*__u32 offset_xi:11;
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__u32 res5:5;
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__u32 offset_yi:11;
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__u32 res6:5;
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*/
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__le32 offset_xyi;
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/* Word 5(32-bit) in DDR memory */
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/*__u32 offset_xd:11;
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__u32 res7:5;
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__u32 offset_yd:11;
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__u32 res8:5; */
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__le32 offset_xyd;
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/* Word 6(32-bit) in DDR memory */
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__u8 ckmax_r;
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__u8 ckmax_g;
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__u8 ckmax_b;
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__u8 res9;
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/* Word 7(32-bit) in DDR memory */
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__u8 ckmin_r;
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__u8 ckmin_g;
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__u8 ckmin_b;
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__u8 res10;
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/* __u32 res10:8; */
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/* Word 8(32-bit) in DDR memory */
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__le32 next_ad;
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/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
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__u32 paddr;
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} __attribute__ ((packed));
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/* DIU register map */
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struct diu {
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__be32 desc[3];
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__be32 gamma;
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__be32 pallete;
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__be32 cursor;
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__be32 curs_pos;
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__be32 diu_mode;
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__be32 bgnd;
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__be32 bgnd_wb;
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__be32 disp_size;
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__be32 wb_size;
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__be32 wb_mem_addr;
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__be32 hsyn_para;
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__be32 vsyn_para;
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__be32 syn_pol;
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__be32 thresholds;
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__be32 int_status;
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__be32 int_mask;
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__be32 colorbar[8];
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__be32 filling;
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__be32 plut;
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} __attribute__ ((packed));
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struct diu_hw {
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struct diu *diu_reg;
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spinlock_t reg_lock;
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__u32 mode; /* DIU operation mode */
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};
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struct diu_addr {
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__u8 __iomem *vaddr; /* Virtual address */
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dma_addr_t paddr; /* Physical address */
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__u32 offset;
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};
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struct diu_pool {
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struct diu_addr ad;
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struct diu_addr gamma;
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struct diu_addr pallete;
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struct diu_addr cursor;
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};
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#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */
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#define INT_LCDC 64 /* DIU interrupt number */
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#define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
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/* 1 for plane 0, 2 for plane 1&2 each */
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/* Minimum X and Y resolutions */
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#define MIN_XRES 64
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#define MIN_YRES 64
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/* HW cursor parameters */
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#define MAX_CURS 32
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/* Modes of operation of DIU */
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#define MFB_MODE0 0 /* DIU off */
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#define MFB_MODE1 1 /* All three planes output to display */
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#define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/
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#define MFB_MODE3 3 /* All three planes written back to memory */
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#define MFB_MODE4 4 /* Color bar generation */
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/* INT_STATUS/INT_MASK field descriptions */
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#define INT_VSYNC 0x01 /* Vsync interrupt */
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#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
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#define INT_UNDRUN 0x04 /* Under run exception interrupt */
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#define INT_PARERR 0x08 /* Display parameters error interrupt */
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#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
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/* Panels'operation modes */
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#define MFB_TYPE_OUTPUT 0 /* Panel output to display */
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#define MFB_TYPE_OFF 1 /* Panel off */
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#define MFB_TYPE_WB 2 /* Panel written back to memory */
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#define MFB_TYPE_TEST 3 /* Panel generate color bar */
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#endif /* __KERNEL__ */
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#endif /* __FSL_DIU_FB_H__ */
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