linux-stable/drivers/clk/davinci
Stephen Boyd b2ac878acd Merge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'clk-davinci' and 'clk-meson' into clk-next
* clk-davinci-psc-da830:
  clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration

* clk-renesas:
  clk: renesas: cpg-mssr: Add support for R-Car E3
  clk: renesas: Add r8a77990 CPG Core Clock Definitions
  clk: renesas: rcar-gen2: Centralize quirks handling
  clk: renesas: r8a77980: Correct parent clock of PCIEC0
  clk: renesas: r8a7794: Fix LB clock divider
  clk: renesas: r8a7792: Fix LB clock divider
  clk: renesas: r8a7791/r8a7793: Fix LB clock divider
  clk: renesas: r8a7745: Fix LB clock divider
  clk: renesas: r8a7743: Fix LB clock divider
  clk: renesas: cpg-mssr: Add r8a77470 support
  clk: renesas: Add r8a77470 CPG Core Clock Definitions
  clk: renesas: r8a77965: Add MSIOF controller clocks

* clk-at91-recalc:
  clk: at91: PLL recalc_rate() now using cached MUL and DIV values

* clk-davinci:
  clk: davinci: Fix link errors when not all SoCs are enabled
  clk: davinci: psc: allow for dev == NULL
  clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE
  clk: davinci: pll: allow dev == NULL
  clk: davinci: psc-dm365: fix few clocks
  clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
  clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups
  clk: davinci: pll-dm355: fix SYSCLKn parent names
  clk: davinci: pll-dm355: drop pll2_sysclk2

* clk-meson:
  clk: meson: axg: let mpll clocks round closest
  clk: meson: mpll: add round closest support
  clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
  clk: meson: use SPDX license identifiers consistently
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson-axg: Add AO Clock and Reset controller driver
  clk: meson: aoclk: refactor common code into dedicated file
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  clk: meson: gxbb: add the video decoder clocks
  clk: meson: meson8b: add support for the NAND clocks
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
  dt-bindings: clock: meson8b: export the NAND clock
2018-06-04 12:37:41 -07:00
..
da8xx-cfgchip.c clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks 2018-03-20 10:16:26 -07:00
Makefile clk: davinci: New driver for TI DA8XX CFGCHIP clocks 2018-03-20 10:16:26 -07:00
pll-da830.c clk: davinci: pll: allow dev == NULL 2018-05-30 12:48:35 -07:00
pll-da850.c clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE 2018-05-30 12:48:39 -07:00
pll-dm355.c clk: davinci: pll: allow dev == NULL 2018-05-30 12:48:35 -07:00
pll-dm365.c clk: davinci: pll: allow dev == NULL 2018-05-30 12:48:35 -07:00
pll-dm644x.c clk: davinci: pll: allow dev == NULL 2018-05-30 12:48:35 -07:00
pll-dm646x.c clk: davinci: pll: allow dev == NULL 2018-05-30 12:48:35 -07:00
pll.c Merge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'clk-davinci' and 'clk-meson' into clk-next 2018-06-04 12:37:41 -07:00
pll.h clk: davinci: Fix link errors when not all SoCs are enabled 2018-05-30 12:48:49 -07:00
psc-da830.c clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration 2018-05-15 15:33:52 -07:00
psc-da850.c clk: davinci: add a reset lookup table for psc0 2018-04-06 13:37:19 -07:00
psc-dm355.c clk: davinci: psc: allow for dev == NULL 2018-05-30 12:48:44 -07:00
psc-dm365.c clk: davinci: psc: allow for dev == NULL 2018-05-30 12:48:44 -07:00
psc-dm644x.c clk: davinci: psc: allow for dev == NULL 2018-05-30 12:48:44 -07:00
psc-dm646x.c clk: davinci: psc: allow for dev == NULL 2018-05-30 12:48:44 -07:00
psc.c clk: davinci: Fix link errors when not all SoCs are enabled 2018-05-30 12:48:49 -07:00
psc.h clk: davinci: Fix link errors when not all SoCs are enabled 2018-05-30 12:48:49 -07:00