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3b67262307
The buck9 regulator of S2MPS11 PMIC had incorrect vsel_mask (0xff instead of 0x1f) thus reading entire register as buck9's voltage. This effectively caused regulator core to interpret values as higher voltages than they were and then to set real voltage much lower than intended. The buck9 provides power to other regulators, including LDO13 and LDO19 which supply the MMC2 (SD card). On Odroid XU3/XU4 the lower voltage caused SD card detection errors on Odroid XU3/XU4: mmc1: card never left busy state mmc1: error -110 whilst initialising SD card During driver probe the regulator core was checking whether initial voltage matches the constraints. With incorrect vsel_mask of 0xff and default value of 0x50, the core interpreted this as 5 V which is outside of constraints (3-3.775 V). Then the regulator core was adjusting the voltage to match the constraints. With incorrect vsel_mask this new voltage mapped to a vere low voltage in the driver. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: <stable@vger.kernel.org>
198 lines
4.3 KiB
C
198 lines
4.3 KiB
C
/*
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* s2mps11.h
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_S2MPS11_H
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#define __LINUX_MFD_S2MPS11_H
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/* S2MPS11 registers */
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enum s2mps11_reg {
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S2MPS11_REG_ID,
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S2MPS11_REG_INT1,
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S2MPS11_REG_INT2,
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S2MPS11_REG_INT3,
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S2MPS11_REG_INT1M,
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S2MPS11_REG_INT2M,
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S2MPS11_REG_INT3M,
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S2MPS11_REG_ST1,
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S2MPS11_REG_ST2,
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S2MPS11_REG_OFFSRC,
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S2MPS11_REG_PWRONSRC,
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S2MPS11_REG_RTC_CTRL,
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S2MPS11_REG_CTRL1,
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S2MPS11_REG_ETC_TEST,
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S2MPS11_REG_RSVD3,
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S2MPS11_REG_BU_CHG,
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S2MPS11_REG_RAMP,
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S2MPS11_REG_RAMP_BUCK,
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S2MPS11_REG_LDO1_8,
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S2MPS11_REG_LDO9_16,
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S2MPS11_REG_LDO17_24,
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S2MPS11_REG_LDO25_32,
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S2MPS11_REG_LDO33_38,
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S2MPS11_REG_LDO1_8_1,
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S2MPS11_REG_LDO9_16_1,
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S2MPS11_REG_LDO17_24_1,
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S2MPS11_REG_LDO25_32_1,
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S2MPS11_REG_LDO33_38_1,
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S2MPS11_REG_OTP_ADRL,
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S2MPS11_REG_OTP_ADRH,
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S2MPS11_REG_OTP_DATA,
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S2MPS11_REG_MON1SEL,
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S2MPS11_REG_MON2SEL,
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S2MPS11_REG_LEE,
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S2MPS11_REG_RSVD_NO,
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S2MPS11_REG_UVLO,
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S2MPS11_REG_LEE_NO,
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S2MPS11_REG_B1CTRL1,
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S2MPS11_REG_B1CTRL2,
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S2MPS11_REG_B2CTRL1,
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S2MPS11_REG_B2CTRL2,
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S2MPS11_REG_B3CTRL1,
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S2MPS11_REG_B3CTRL2,
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S2MPS11_REG_B4CTRL1,
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S2MPS11_REG_B4CTRL2,
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S2MPS11_REG_B5CTRL1,
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S2MPS11_REG_BUCK5_SW,
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S2MPS11_REG_B5CTRL2,
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S2MPS11_REG_B5CTRL3,
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S2MPS11_REG_B5CTRL4,
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S2MPS11_REG_B5CTRL5,
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S2MPS11_REG_B6CTRL1,
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S2MPS11_REG_B6CTRL2,
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S2MPS11_REG_B7CTRL1,
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S2MPS11_REG_B7CTRL2,
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S2MPS11_REG_B8CTRL1,
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S2MPS11_REG_B8CTRL2,
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S2MPS11_REG_B9CTRL1,
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S2MPS11_REG_B9CTRL2,
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S2MPS11_REG_B10CTRL1,
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S2MPS11_REG_B10CTRL2,
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S2MPS11_REG_L1CTRL,
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S2MPS11_REG_L2CTRL,
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S2MPS11_REG_L3CTRL,
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S2MPS11_REG_L4CTRL,
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S2MPS11_REG_L5CTRL,
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S2MPS11_REG_L6CTRL,
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S2MPS11_REG_L7CTRL,
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S2MPS11_REG_L8CTRL,
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S2MPS11_REG_L9CTRL,
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S2MPS11_REG_L10CTRL,
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S2MPS11_REG_L11CTRL,
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S2MPS11_REG_L12CTRL,
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S2MPS11_REG_L13CTRL,
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S2MPS11_REG_L14CTRL,
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S2MPS11_REG_L15CTRL,
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S2MPS11_REG_L16CTRL,
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S2MPS11_REG_L17CTRL,
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S2MPS11_REG_L18CTRL,
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S2MPS11_REG_L19CTRL,
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S2MPS11_REG_L20CTRL,
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S2MPS11_REG_L21CTRL,
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S2MPS11_REG_L22CTRL,
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S2MPS11_REG_L23CTRL,
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S2MPS11_REG_L24CTRL,
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S2MPS11_REG_L25CTRL,
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S2MPS11_REG_L26CTRL,
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S2MPS11_REG_L27CTRL,
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S2MPS11_REG_L28CTRL,
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S2MPS11_REG_L29CTRL,
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S2MPS11_REG_L30CTRL,
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S2MPS11_REG_L31CTRL,
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S2MPS11_REG_L32CTRL,
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S2MPS11_REG_L33CTRL,
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S2MPS11_REG_L34CTRL,
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S2MPS11_REG_L35CTRL,
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S2MPS11_REG_L36CTRL,
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S2MPS11_REG_L37CTRL,
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S2MPS11_REG_L38CTRL,
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};
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/* S2MPS11 regulator ids */
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enum s2mps11_regulators {
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S2MPS11_LDO1,
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S2MPS11_LDO2,
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S2MPS11_LDO3,
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S2MPS11_LDO4,
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S2MPS11_LDO5,
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S2MPS11_LDO6,
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S2MPS11_LDO7,
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S2MPS11_LDO8,
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S2MPS11_LDO9,
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S2MPS11_LDO10,
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S2MPS11_LDO11,
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S2MPS11_LDO12,
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S2MPS11_LDO13,
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S2MPS11_LDO14,
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S2MPS11_LDO15,
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S2MPS11_LDO16,
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S2MPS11_LDO17,
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S2MPS11_LDO18,
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S2MPS11_LDO19,
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S2MPS11_LDO20,
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S2MPS11_LDO21,
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S2MPS11_LDO22,
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S2MPS11_LDO23,
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S2MPS11_LDO24,
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S2MPS11_LDO25,
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S2MPS11_LDO26,
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S2MPS11_LDO27,
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S2MPS11_LDO28,
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S2MPS11_LDO29,
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S2MPS11_LDO30,
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S2MPS11_LDO31,
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S2MPS11_LDO32,
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S2MPS11_LDO33,
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S2MPS11_LDO34,
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S2MPS11_LDO35,
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S2MPS11_LDO36,
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S2MPS11_LDO37,
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S2MPS11_LDO38,
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S2MPS11_BUCK1,
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S2MPS11_BUCK2,
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S2MPS11_BUCK3,
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S2MPS11_BUCK4,
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S2MPS11_BUCK5,
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S2MPS11_BUCK6,
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S2MPS11_BUCK7,
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S2MPS11_BUCK8,
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S2MPS11_BUCK9,
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S2MPS11_BUCK10,
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S2MPS11_REGULATOR_MAX,
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};
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#define S2MPS11_LDO_VSEL_MASK 0x3F
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#define S2MPS11_BUCK_VSEL_MASK 0xFF
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#define S2MPS11_BUCK9_VSEL_MASK 0x1F
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#define S2MPS11_ENABLE_MASK (0x03 << S2MPS11_ENABLE_SHIFT)
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#define S2MPS11_ENABLE_SHIFT 0x06
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#define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1)
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#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1)
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#define S2MPS11_BUCK9_N_VOLTAGES (S2MPS11_BUCK9_VSEL_MASK + 1)
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#define S2MPS11_RAMP_DELAY 25000 /* uV/us */
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#define S2MPS11_CTRL1_PWRHOLD_MASK BIT(4)
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#define S2MPS11_BUCK2_RAMP_SHIFT 6
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#define S2MPS11_BUCK34_RAMP_SHIFT 4
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#define S2MPS11_BUCK5_RAMP_SHIFT 6
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#define S2MPS11_BUCK16_RAMP_SHIFT 4
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#define S2MPS11_BUCK7810_RAMP_SHIFT 2
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#define S2MPS11_BUCK9_RAMP_SHIFT 0
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#define S2MPS11_BUCK2_RAMP_EN_SHIFT 3
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#define S2MPS11_BUCK3_RAMP_EN_SHIFT 2
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#define S2MPS11_BUCK4_RAMP_EN_SHIFT 1
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#define S2MPS11_BUCK6_RAMP_EN_SHIFT 0
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#define S2MPS11_PMIC_EN_SHIFT 6
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#endif /* __LINUX_MFD_S2MPS11_H */
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