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9e4808d2c6
Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15 PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz clock outputs and battery charger. This patch adds initial support for LDO and buck regulators of S2MPS15 device. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [Alim: Added s2mps15_devs like rtc and clk and related changes] Signed-off-by: Lee Jones <lee.jones@linaro.org>
158 lines
3.4 KiB
C
158 lines
3.4 KiB
C
/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_MFD_S2MPS15_H
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#define __LINUX_MFD_S2MPS15_H
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/* S2MPS15 registers */
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enum s2mps15_reg {
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S2MPS15_REG_ID,
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S2MPS15_REG_INT1,
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S2MPS15_REG_INT2,
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S2MPS15_REG_INT3,
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S2MPS15_REG_INT1M,
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S2MPS15_REG_INT2M,
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S2MPS15_REG_INT3M,
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S2MPS15_REG_ST1,
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S2MPS15_REG_ST2,
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S2MPS15_REG_PWRONSRC,
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S2MPS15_REG_OFFSRC,
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S2MPS15_REG_BU_CHG,
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S2MPS15_REG_RTC_BUF,
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S2MPS15_REG_CTRL1,
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S2MPS15_REG_CTRL2,
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S2MPS15_REG_RSVD1,
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S2MPS15_REG_RSVD2,
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S2MPS15_REG_RSVD3,
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S2MPS15_REG_RSVD4,
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S2MPS15_REG_RSVD5,
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S2MPS15_REG_RSVD6,
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S2MPS15_REG_CTRL3,
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S2MPS15_REG_RSVD7,
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S2MPS15_REG_RSVD8,
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S2MPS15_REG_RSVD9,
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S2MPS15_REG_B1CTRL1,
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S2MPS15_REG_B1CTRL2,
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S2MPS15_REG_B2CTRL1,
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S2MPS15_REG_B2CTRL2,
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S2MPS15_REG_B3CTRL1,
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S2MPS15_REG_B3CTRL2,
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S2MPS15_REG_B4CTRL1,
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S2MPS15_REG_B4CTRL2,
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S2MPS15_REG_B5CTRL1,
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S2MPS15_REG_B5CTRL2,
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S2MPS15_REG_B6CTRL1,
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S2MPS15_REG_B6CTRL2,
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S2MPS15_REG_B7CTRL1,
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S2MPS15_REG_B7CTRL2,
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S2MPS15_REG_B8CTRL1,
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S2MPS15_REG_B8CTRL2,
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S2MPS15_REG_B9CTRL1,
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S2MPS15_REG_B9CTRL2,
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S2MPS15_REG_B10CTRL1,
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S2MPS15_REG_B10CTRL2,
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S2MPS15_REG_BBCTRL1,
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S2MPS15_REG_BBCTRL2,
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S2MPS15_REG_BRAMP,
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S2MPS15_REG_LDODVS1,
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S2MPS15_REG_LDODVS2,
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S2MPS15_REG_LDODVS3,
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S2MPS15_REG_LDODVS4,
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S2MPS15_REG_L1CTRL,
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S2MPS15_REG_L2CTRL,
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S2MPS15_REG_L3CTRL,
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S2MPS15_REG_L4CTRL,
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S2MPS15_REG_L5CTRL,
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S2MPS15_REG_L6CTRL,
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S2MPS15_REG_L7CTRL,
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S2MPS15_REG_L8CTRL,
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S2MPS15_REG_L9CTRL,
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S2MPS15_REG_L10CTRL,
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S2MPS15_REG_L11CTRL,
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S2MPS15_REG_L12CTRL,
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S2MPS15_REG_L13CTRL,
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S2MPS15_REG_L14CTRL,
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S2MPS15_REG_L15CTRL,
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S2MPS15_REG_L16CTRL,
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S2MPS15_REG_L17CTRL,
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S2MPS15_REG_L18CTRL,
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S2MPS15_REG_L19CTRL,
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S2MPS15_REG_L20CTRL,
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S2MPS15_REG_L21CTRL,
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S2MPS15_REG_L22CTRL,
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S2MPS15_REG_L23CTRL,
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S2MPS15_REG_L24CTRL,
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S2MPS15_REG_L25CTRL,
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S2MPS15_REG_L26CTRL,
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S2MPS15_REG_L27CTRL,
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S2MPS15_REG_LDODSCH1,
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S2MPS15_REG_LDODSCH2,
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S2MPS15_REG_LDODSCH3,
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S2MPS15_REG_LDODSCH4,
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};
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/* S2MPS15 regulator ids */
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enum s2mps15_regulators {
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S2MPS15_LDO1,
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S2MPS15_LDO2,
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S2MPS15_LDO3,
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S2MPS15_LDO4,
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S2MPS15_LDO5,
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S2MPS15_LDO6,
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S2MPS15_LDO7,
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S2MPS15_LDO8,
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S2MPS15_LDO9,
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S2MPS15_LDO10,
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S2MPS15_LDO11,
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S2MPS15_LDO12,
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S2MPS15_LDO13,
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S2MPS15_LDO14,
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S2MPS15_LDO15,
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S2MPS15_LDO16,
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S2MPS15_LDO17,
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S2MPS15_LDO18,
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S2MPS15_LDO19,
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S2MPS15_LDO20,
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S2MPS15_LDO21,
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S2MPS15_LDO22,
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S2MPS15_LDO23,
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S2MPS15_LDO24,
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S2MPS15_LDO25,
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S2MPS15_LDO26,
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S2MPS15_LDO27,
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S2MPS15_BUCK1,
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S2MPS15_BUCK2,
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S2MPS15_BUCK3,
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S2MPS15_BUCK4,
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S2MPS15_BUCK5,
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S2MPS15_BUCK6,
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S2MPS15_BUCK7,
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S2MPS15_BUCK8,
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S2MPS15_BUCK9,
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S2MPS15_BUCK10,
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S2MPS15_BUCK11,
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S2MPS15_REGULATOR_MAX,
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};
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#define S2MPS15_LDO_VSEL_MASK (0x3F)
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#define S2MPS15_BUCK_VSEL_MASK (0xFF)
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#define S2MPS15_ENABLE_SHIFT (0x06)
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#define S2MPS15_ENABLE_MASK (0x03 << S2MPS15_ENABLE_SHIFT)
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#define S2MPS15_LDO_N_VOLTAGES (S2MPS15_LDO_VSEL_MASK + 1)
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#define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)
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#endif /* __LINUX_MFD_S2MPS15_H */
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