Russell King b2c3e38a54 ARM: redo TTBR setup code for LPAE ... Re-engineer the LPAE TTBR setup code. Rather than passing some shifted address in order to fit in a CPU register, pass either a full physical address (in the case of r4, r5 for TTBR0) or a PFN (for TTBR1). This removes the ARCH_PGD_SHIFT hack, and the last dangerous user of cpu_set_ttbr() in the secondary CPU startup code path (which was there to re-set TTBR1 to the appropriate high physical address space on Keystone2.) Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2015-06-01 23:48:19 +01:00
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Kconfig	ARM: keystone: add pcie related options	2014-11-04 10:29:39 -08:00
keystone.c	ARM: keystone2: rename init_meminfo to pv_fixup	2015-06-01 23:45:56 +01:00
keystone.h	ARM: keystone: Make PM bus ready before populating platform devices	2013-12-16 16:03:36 -05:00
Makefile	ARM: keystone: add PM domain support for clock management	2013-10-10 19:51:19 -04:00
Makefile.boot
memory.h	ARM: keystone: Switch over to coherent memory address space	2014-05-08 15:43:33 -04:00
platsmp.c	ARM: redo TTBR setup code for LPAE	2015-06-01 23:48:19 +01:00
pm_domain.c	ARM: make of_device_ids const	2015-02-19 09:44:25 +01:00
smc.S	ARM: keystone: Drop the un-necessary dsb from keystone_cpu_smc()	2013-08-05 13:22:09 -04:00