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8857433245
Add support for the AES/SM4 crypto engine included in the Offload and Crypto Subsystem (OCS) of the Intel Keem Bay SoC, thus enabling hardware-acceleration for the following transformations: - ecb(aes), cbc(aes), ctr(aes), cts(cbc(aes)), gcm(aes) and cbc(aes); supported for 128-bit and 256-bit keys. - ecb(sm4), cbc(sm4), ctr(sm4), cts(cbc(sm4)), gcm(sm4) and cbc(sm4); supported for 128-bit keys. The driver passes crypto manager self-tests, including the extra tests (CRYPTO_MANAGER_EXTRA_TESTS=y). Signed-off-by: Mike Healy <mikex.healy@intel.com> Co-developed-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com> Acked-by: Mark Gross <mgross@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Keem Bay OCS AES Crypto Driver.
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*
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* Copyright (C) 2018-2020 Intel Corporation
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*/
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#ifndef _CRYPTO_OCS_AES_H
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#define _CRYPTO_OCS_AES_H
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#include <linux/dma-mapping.h>
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enum ocs_cipher {
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OCS_AES = 0,
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OCS_SM4 = 1,
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};
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enum ocs_mode {
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OCS_MODE_ECB = 0,
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OCS_MODE_CBC = 1,
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OCS_MODE_CTR = 2,
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OCS_MODE_CCM = 6,
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OCS_MODE_GCM = 7,
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OCS_MODE_CTS = 9,
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};
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enum ocs_instruction {
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OCS_ENCRYPT = 0,
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OCS_DECRYPT = 1,
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OCS_EXPAND = 2,
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OCS_BYPASS = 3,
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};
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/**
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* struct ocs_aes_dev - AES device context.
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* @list: List head for insertion into device list hold
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* by driver.
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* @dev: OCS AES device.
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* @irq: IRQ number.
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* @base_reg: IO base address of OCS AES.
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* @irq_copy_completion: Completion to indicate IRQ has been triggered.
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* @dma_err_mask: Error reported by OCS DMA interrupts.
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* @engine: Crypto engine for the device.
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*/
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struct ocs_aes_dev {
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struct list_head list;
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struct device *dev;
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int irq;
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void __iomem *base_reg;
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struct completion irq_completion;
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u32 dma_err_mask;
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struct crypto_engine *engine;
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};
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/**
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* struct ocs_dll_desc - Descriptor of an OCS DMA Linked List.
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* @vaddr: Virtual address of the linked list head.
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* @dma_addr: DMA address of the linked list head.
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* @size: Size (in bytes) of the linked list.
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*/
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struct ocs_dll_desc {
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void *vaddr;
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dma_addr_t dma_addr;
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size_t size;
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};
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int ocs_aes_set_key(struct ocs_aes_dev *aes_dev, const u32 key_size,
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const u8 *key, const enum ocs_cipher cipher);
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int ocs_aes_op(struct ocs_aes_dev *aes_dev,
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enum ocs_mode mode,
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enum ocs_cipher cipher,
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enum ocs_instruction instruction,
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dma_addr_t dst_dma_list,
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dma_addr_t src_dma_list,
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u32 src_size,
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u8 *iv,
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u32 iv_size);
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/**
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* ocs_aes_bypass_op() - Use OCS DMA to copy data.
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* @aes_dev: The OCS AES device to use.
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* @dst_dma_list: The OCS DMA list mapping the memory where input data
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* will be copied to.
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* @src_dma_list: The OCS DMA list mapping input data.
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* @src_size: The amount of data to copy.
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*/
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static inline int ocs_aes_bypass_op(struct ocs_aes_dev *aes_dev,
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dma_addr_t dst_dma_list,
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dma_addr_t src_dma_list, u32 src_size)
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{
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return ocs_aes_op(aes_dev, OCS_MODE_ECB, OCS_AES, OCS_BYPASS,
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dst_dma_list, src_dma_list, src_size, NULL, 0);
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}
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int ocs_aes_gcm_op(struct ocs_aes_dev *aes_dev,
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enum ocs_cipher cipher,
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enum ocs_instruction instruction,
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dma_addr_t dst_dma_list,
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dma_addr_t src_dma_list,
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u32 src_size,
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const u8 *iv,
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dma_addr_t aad_dma_list,
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u32 aad_size,
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u8 *out_tag,
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u32 tag_size);
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int ocs_aes_ccm_op(struct ocs_aes_dev *aes_dev,
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enum ocs_cipher cipher,
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enum ocs_instruction instruction,
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dma_addr_t dst_dma_list,
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dma_addr_t src_dma_list,
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u32 src_size,
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u8 *iv,
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dma_addr_t adata_dma_list,
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u32 adata_size,
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u8 *in_tag,
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u32 tag_size);
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int ocs_create_linked_list_from_sg(const struct ocs_aes_dev *aes_dev,
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struct scatterlist *sg,
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int sg_dma_count,
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struct ocs_dll_desc *dll_desc,
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size_t data_size,
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size_t data_offset);
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irqreturn_t ocs_aes_irq_handler(int irq, void *dev_id);
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#endif
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