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![Ralf Baechle](/assets/img/avatar_default.png)
initialization actually useful and as is certainly unmergable with upstream. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
401 lines
11 KiB
C
401 lines
11 KiB
C
/*
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* arch/mips/ddb5xxx/ddb5477/setup.c
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* Setup file for DDB5477.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/fs.h>
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#include <linux/ioport.h>
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#include <linux/param.h> /* for HZ */
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#include <linux/major.h>
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#include <linux/kdev_t.h>
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#include <linux/root_dev.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/addrspace.h>
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#include <asm/time.h>
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#include <asm/bcache.h>
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#include <asm/irq.h>
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#include <asm/reboot.h>
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#include <asm/gdb-stub.h>
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#include <asm/traps.h>
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#include <asm/debug.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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#include "lcd44780.h"
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#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
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#define SP_TIMER_BASE DDB_SPT1CTRL_L
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#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
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static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
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static void ddb_machine_restart(char *command)
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{
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static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
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u32 t;
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/* PCI cold reset */
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ddb_pci_reset_bus();
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/* CPU cold reset */
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t = ddb_in32(DDB_CPUSTAT);
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db_assert((t&1));
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ddb_out32(DDB_CPUSTAT, t);
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/* Call the PROM */
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back_to_prom();
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}
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static void ddb_machine_halt(void)
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{
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printk("DDB Vrc-5477 halted.\n");
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while (1);
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}
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static void ddb_machine_power_off(void)
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{
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printk("DDB Vrc-5477 halted. Please turn off the power.\n");
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while (1);
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}
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extern void rtc_ds1386_init(unsigned long base);
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static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
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{
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unsigned int freq;
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unsigned char c;
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unsigned int t1, t2;
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unsigned i;
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ddb_out32(SP_TIMER_BASE, 0xffffffff);
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ddb_out32(SP_TIMER_BASE+4, 0x1);
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ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
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/* check if rtc is running */
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c= *(volatile unsigned char*)rtc_base;
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for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
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if (c == *(volatile unsigned char*)rtc_base) {
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printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
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return 83333000;
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}
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c= *(volatile unsigned char*)rtc_base;
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while (c == *(volatile unsigned char*)rtc_base);
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/* we are now at the turn of 1/100th second, if no error. */
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t1 = ddb_in32(SP_TIMER_BASE+8);
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for (i=0; i< 10; i++) {
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c= *(volatile unsigned char*)rtc_base;
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while (c == *(volatile unsigned char*)rtc_base);
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/* we are now at the turn of another 1/100th second */
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t2 = ddb_in32(SP_TIMER_BASE+8);
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}
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ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
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freq = (t1 - t2)*10;
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printk("DDB bus frequency detection : %u \n", freq);
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return freq;
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}
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static void __init ddb_time_init(void)
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{
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unsigned long rtc_base;
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unsigned int i;
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/* we have ds1396 RTC chip */
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if (mips_machtype == MACH_NEC_ROCKHOPPER
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|| mips_machtype == MACH_NEC_ROCKHOPPERII) {
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rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
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} else {
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rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
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}
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rtc_ds1386_init(rtc_base);
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/* do we need to do run-time detection of bus speed? */
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if (bus_frequency == 0) {
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bus_frequency = detect_bus_frequency(rtc_base);
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}
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/* mips_hpt_frequency is 1/2 of the cpu core freq */
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i = (read_c0_config() >> 28 ) & 7;
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if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
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i = 4;
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mips_hpt_frequency = bus_frequency*(i+4)/4;
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}
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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static void __init ddb_timer_setup(struct irqaction *irq)
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{
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#if defined(USE_CPU_COUNTER_TIMER)
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/* we are using the cpu counter for timer interrupts */
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setup_irq(CPU_IRQ_BASE + 7, irq);
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#else
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/* if we use Special purpose timer 1 */
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ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
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ddb_out32(SP_TIMER_BASE+4, 0x1);
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setup_irq(SP_TIMER_IRQ, irq);
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#endif
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}
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static void ddb5477_board_init(void);
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extern struct pci_controller ddb5477_ext_controller;
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extern struct pci_controller ddb5477_io_controller;
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void __init plat_setup(void)
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{
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/* initialize board - we don't trust the loader */
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ddb5477_board_init();
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set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
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board_time_init = ddb_time_init;
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board_timer_setup = ddb_timer_setup;
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_machine_restart = ddb_machine_restart;
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_machine_halt = ddb_machine_halt;
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_machine_power_off = ddb_machine_power_off;
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/* setup resource limits */
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ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
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iomem_resource.end = 0xffffffff;
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/* Reboot on panic */
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panic_timeout = 180;
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register_pci_controller (&ddb5477_ext_controller);
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register_pci_controller (&ddb5477_io_controller);
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}
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static void __init ddb5477_board_init(void)
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{
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/* ----------- setup PDARs ------------ */
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/* SDRAM should have been set */
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db_assert(ddb_in32(DDB_SDRAM0) ==
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ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
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/* SDRAM1 should be turned off. What is this for anyway ? */
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db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
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/* Setup local bus. */
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/* Flash U12 PDAR and timing. */
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ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
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ddb_out32(DDB_LCST0, 0x00090842);
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/* We need to setup LCS1 and LCS2 differently based on the
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board_version */
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if (mips_machtype == MACH_NEC_ROCKHOPPER) {
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/* Flash U13 PDAR and timing. */
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ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
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ddb_out32(DDB_LCST1, 0x00090842);
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/* EPLD (NVRAM, switch, LCD, and mezzanie). */
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ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
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} else {
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/* misc */
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ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
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/* mezzanie (?) */
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ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
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}
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/* verify VRC5477 base addr */
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db_assert(ddb_in32(DDB_VRC5477) ==
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ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
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/* verify BOOT ROM addr */
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db_assert(ddb_in32(DDB_BOOTCS) ==
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ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
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/* setup PCI windows - window0 for MEM/config, window1 for IO */
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ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
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ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
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ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
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ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
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/* ------------ reset PCI bus and BARs ----------------- */
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ddb_pci_reset_bus();
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ddb_out32(DDB_BARM010, 0x00000008);
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ddb_out32(DDB_BARM011, 0x00000008);
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ddb_out32(DDB_BARC0, 0xffffffff);
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ddb_out32(DDB_BARM230, 0xffffffff);
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ddb_out32(DDB_BAR00, 0xffffffff);
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ddb_out32(DDB_BAR10, 0xffffffff);
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ddb_out32(DDB_BAR20, 0xffffffff);
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ddb_out32(DDB_BAR30, 0xffffffff);
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ddb_out32(DDB_BAR40, 0xffffffff);
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ddb_out32(DDB_BAR50, 0xffffffff);
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ddb_out32(DDB_BARB0, 0xffffffff);
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ddb_out32(DDB_BARC1, 0xffffffff);
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ddb_out32(DDB_BARM231, 0xffffffff);
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ddb_out32(DDB_BAR01, 0xffffffff);
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ddb_out32(DDB_BAR11, 0xffffffff);
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ddb_out32(DDB_BAR21, 0xffffffff);
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ddb_out32(DDB_BAR31, 0xffffffff);
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ddb_out32(DDB_BAR41, 0xffffffff);
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ddb_out32(DDB_BAR51, 0xffffffff);
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ddb_out32(DDB_BARB1, 0xffffffff);
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/*
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* We use pci master register 0 for memory space / config space
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* And we use register 1 for IO space.
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* Note that for memory space, we bump up the pci base address
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* so that we have 1:1 mapping between PCI memory and cpu physical.
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* For PCI IO space, it starts from 0 in PCI IO space but with
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* DDB_xx_IO_BASE in CPU physical address space.
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*/
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ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
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DDB_PCI_ACCESS_32);
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ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
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ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
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DDB_PCI_ACCESS_32);
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ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
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DDB_PCI_ACCESS_32);
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/* PCI cross window should be set properly */
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ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
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ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
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ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
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ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
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if (mips_machtype == MACH_NEC_ROCKHOPPER
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|| mips_machtype == MACH_NEC_ROCKHOPPERII) {
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/* Disable bus diagnostics. */
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ddb_out32(DDB_PCICTL0_L, 0);
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ddb_out32(DDB_PCICTL0_H, 0);
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ddb_out32(DDB_PCICTL1_L, 0);
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ddb_out32(DDB_PCICTL1_H, 0);
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}
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if (mips_machtype == MACH_NEC_ROCKHOPPER) {
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u16 vid;
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struct pci_bus bus;
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struct pci_dev dev_m1533;
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extern struct pci_ops ddb5477_ext_pci_ops;
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bus.parent = NULL; /* we scan the top level only */
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bus.ops = &ddb5477_ext_pci_ops;
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dev_m1533.bus = &bus;
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dev_m1533.sysdata = NULL;
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dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
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pci_read_config_word(&dev_m1533, 0, &vid);
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if (vid == PCI_VENDOR_ID_AL) {
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printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
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mips_machtype = MACH_NEC_ROCKHOPPERII;
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}
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}
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/* enable USB input buffers */
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ddb_out32(DDB_PIBMISC, 0x00000007);
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/* For dual-function pins, make them all non-GPIO */
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ddb_out32(DDB_GIUFUNSEL, 0x0);
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// ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
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if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
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/* enable IDE controller on Ali chip (south bridge) */
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u8 temp8;
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struct pci_bus bus;
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struct pci_dev dev_m1533;
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struct pci_dev dev_m5229;
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extern struct pci_ops ddb5477_ext_pci_ops;
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/* Setup M1535 registers */
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bus.parent = NULL; /* we scan the top level only */
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bus.ops = &ddb5477_ext_pci_ops;
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dev_m1533.bus = &bus;
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dev_m1533.sysdata = NULL;
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dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
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/* setup IDE controller
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* enable IDE controller (bit 6 - 1)
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* IDE IDSEL to be addr:A15 (bit 4:5 - 11)
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* disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
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* enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
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*/
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pci_write_config_byte(&dev_m1533, 0x58, 0x74);
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/*
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* positive decode (bit6 -0)
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* enable IDE controler interrupt (bit 4 -1)
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* setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
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*/
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pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
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/* Setup M5229 registers */
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dev_m5229.bus = &bus;
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dev_m5229.sysdata = NULL;
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dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
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/*
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* enable IDE in the M5229 config register 0x50 (bit 0 - 1)
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* M5229 IDSEL is addr:15; see above setting
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*/
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pci_read_config_byte(&dev_m5229, 0x50, &temp8);
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pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
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/*
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* enable bus master (bit 2) and IO decoding (bit 0)
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*/
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pci_read_config_byte(&dev_m5229, 0x04, &temp8);
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pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
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/*
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* enable native, copied from arch/ppc/k2boot/head.S
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* TODO - need volatile, need to be portable
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*/
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pci_write_config_byte(&dev_m5229, 0x09, 0xef);
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/* Set Primary Channel Command Block Timing */
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pci_write_config_byte(&dev_m5229, 0x59, 0x31);
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/*
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* Enable primary channel 40-pin cable
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* M5229 register 0x4a (bit 0)
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*/
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pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
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pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
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}
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if (mips_machtype == MACH_NEC_ROCKHOPPER
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|| mips_machtype == MACH_NEC_ROCKHOPPERII) {
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printk("lcd44780: initializing\n");
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lcd44780_init();
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lcd44780_puts("MontaVista Linux");
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}
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}
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