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![Saravana Kannan](/assets/img/avatar_default.png)
Since this device is only partially initialized by the irqchip driver, we need to mark the fwnode device as not initialized. This is to let fw_devlink know that the device will be completely initialized at a later point. That way, fw_devlink will continue to defer the probe of the power domain consumers till the power domain driver successfully binds to the struct device and completes the initialization of the device. Signed-off-by: Saravana Kannan <saravanak@google.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcom/sm7225-fairphone-fp4 Link: https://lore.kernel.org/r/20230207014207.1678715-11-saravanak@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
291 lines
6.8 KiB
C
291 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <linux/syscore_ops.h>
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#define IMR_NUM 4
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#define GPC_MAX_IRQS (IMR_NUM * 32)
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#define GPC_IMR1_CORE0 0x30
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#define GPC_IMR1_CORE1 0x40
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#define GPC_IMR1_CORE2 0x1c0
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#define GPC_IMR1_CORE3 0x1d0
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struct gpcv2_irqchip_data {
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struct raw_spinlock rlock;
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void __iomem *gpc_base;
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u32 wakeup_sources[IMR_NUM];
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u32 saved_irq_mask[IMR_NUM];
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u32 cpu2wakeup;
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};
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static struct gpcv2_irqchip_data *imx_gpcv2_instance __ro_after_init;
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static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
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{
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return cd->gpc_base + cd->cpu2wakeup + i * 4;
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}
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static int gpcv2_wakeup_source_save(void)
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{
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struct gpcv2_irqchip_data *cd;
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void __iomem *reg;
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int i;
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cd = imx_gpcv2_instance;
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if (!cd)
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return 0;
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for (i = 0; i < IMR_NUM; i++) {
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reg = gpcv2_idx_to_reg(cd, i);
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cd->saved_irq_mask[i] = readl_relaxed(reg);
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writel_relaxed(cd->wakeup_sources[i], reg);
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}
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return 0;
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}
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static void gpcv2_wakeup_source_restore(void)
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{
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struct gpcv2_irqchip_data *cd;
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int i;
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cd = imx_gpcv2_instance;
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if (!cd)
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return;
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
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}
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static struct syscore_ops imx_gpcv2_syscore_ops = {
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.suspend = gpcv2_wakeup_source_save,
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.resume = gpcv2_wakeup_source_restore,
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};
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static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct gpcv2_irqchip_data *cd = d->chip_data;
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unsigned int idx = d->hwirq / 32;
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unsigned long flags;
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u32 mask, val;
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raw_spin_lock_irqsave(&cd->rlock, flags);
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mask = BIT(d->hwirq % 32);
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val = cd->wakeup_sources[idx];
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cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
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raw_spin_unlock_irqrestore(&cd->rlock, flags);
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/*
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* Do *not* call into the parent, as the GIC doesn't have any
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* wake-up facility...
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*/
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return 0;
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}
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static void imx_gpcv2_irq_unmask(struct irq_data *d)
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{
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struct gpcv2_irqchip_data *cd = d->chip_data;
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void __iomem *reg;
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u32 val;
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raw_spin_lock(&cd->rlock);
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reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
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val = readl_relaxed(reg);
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val &= ~BIT(d->hwirq % 32);
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writel_relaxed(val, reg);
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raw_spin_unlock(&cd->rlock);
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irq_chip_unmask_parent(d);
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}
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static void imx_gpcv2_irq_mask(struct irq_data *d)
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{
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struct gpcv2_irqchip_data *cd = d->chip_data;
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void __iomem *reg;
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u32 val;
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raw_spin_lock(&cd->rlock);
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reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
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val = readl_relaxed(reg);
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val |= BIT(d->hwirq % 32);
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writel_relaxed(val, reg);
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raw_spin_unlock(&cd->rlock);
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irq_chip_mask_parent(d);
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}
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static struct irq_chip gpcv2_irqchip_data_chip = {
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.name = "GPCv2",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = imx_gpcv2_irq_mask,
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.irq_unmask = imx_gpcv2_irq_unmask,
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.irq_set_wake = imx_gpcv2_irq_set_wake,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = irq_chip_set_type_parent,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int imx_gpcv2_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
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unsigned int irq, unsigned int nr_irqs,
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void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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unsigned int type;
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int err;
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int i;
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err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type);
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if (err)
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return err;
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if (hwirq >= GPC_MAX_IRQS)
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return -EINVAL;
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for (i = 0; i < nr_irqs; i++) {
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irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
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&gpcv2_irqchip_data_chip, domain->host_data);
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}
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
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.translate = imx_gpcv2_domain_translate,
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.alloc = imx_gpcv2_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static const struct of_device_id gpcv2_of_match[] = {
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{ .compatible = "fsl,imx7d-gpc", .data = (const void *) 2 },
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{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
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{ /* END */ }
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};
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static int __init imx_gpcv2_irqchip_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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struct gpcv2_irqchip_data *cd;
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const struct of_device_id *id;
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unsigned long core_num;
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int i;
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if (!parent) {
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pr_err("%pOF: no parent, giving up\n", node);
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return -ENODEV;
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}
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id = of_match_node(gpcv2_of_match, node);
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if (!id) {
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pr_err("%pOF: unknown compatibility string\n", node);
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return -ENODEV;
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}
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core_num = (unsigned long)id->data;
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%pOF: unable to get parent domain\n", node);
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return -ENXIO;
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}
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cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
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if (!cd)
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return -ENOMEM;
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raw_spin_lock_init(&cd->rlock);
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cd->gpc_base = of_iomap(node, 0);
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if (!cd->gpc_base) {
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pr_err("%pOF: unable to map gpc registers\n", node);
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kfree(cd);
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return -ENOMEM;
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}
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domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
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node, &gpcv2_irqchip_data_domain_ops, cd);
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if (!domain) {
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iounmap(cd->gpc_base);
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kfree(cd);
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return -ENOMEM;
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}
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irq_set_default_host(domain);
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/* Initially mask all interrupts */
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for (i = 0; i < IMR_NUM; i++) {
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void __iomem *reg = cd->gpc_base + i * 4;
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switch (core_num) {
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case 4:
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writel_relaxed(~0, reg + GPC_IMR1_CORE2);
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writel_relaxed(~0, reg + GPC_IMR1_CORE3);
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fallthrough;
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case 2:
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writel_relaxed(~0, reg + GPC_IMR1_CORE0);
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writel_relaxed(~0, reg + GPC_IMR1_CORE1);
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}
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cd->wakeup_sources[i] = ~0;
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}
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/* Let CORE0 as the default CPU to wake up by GPC */
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cd->cpu2wakeup = GPC_IMR1_CORE0;
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/*
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* Due to hardware design failure, need to make sure GPR
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* interrupt(#32) is unmasked during RUN mode to avoid entering
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* DSM by mistake.
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*/
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writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
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imx_gpcv2_instance = cd;
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register_syscore_ops(&imx_gpcv2_syscore_ops);
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/*
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* Clear the OF_POPULATED flag set in of_irq_init so that
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* later the GPC power domain driver will not be skipped.
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*/
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of_node_clear_flag(node, OF_POPULATED);
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fwnode_dev_initialized(domain->fwnode, false);
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return 0;
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}
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IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
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IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);
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