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![Huacai Chen](/assets/img/avatar_default.png)
Add suspend/resume support for PCH-LPC irqchip, which is needed for upcoming suspend/hibernation. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221020073527.541845-5-chenhuacai@loongson.cn
230 lines
5.5 KiB
C
230 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Loongson LPC Interrupt Controller support
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#define pr_fmt(fmt) "lpc: " fmt
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/syscore_ops.h>
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/* Registers */
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#define LPC_INT_CTL 0x00
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#define LPC_INT_ENA 0x04
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#define LPC_INT_STS 0x08
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#define LPC_INT_CLR 0x0c
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#define LPC_INT_POL 0x10
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#define LPC_COUNT 16
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/* LPC_INT_CTL */
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#define LPC_INT_CTL_EN BIT(31)
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struct pch_lpc {
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void __iomem *base;
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struct irq_domain *lpc_domain;
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raw_spinlock_t lpc_lock;
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u32 saved_reg_ctl;
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u32 saved_reg_ena;
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u32 saved_reg_pol;
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};
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static struct pch_lpc *pch_lpc_priv;
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struct fwnode_handle *pch_lpc_handle;
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static void lpc_irq_ack(struct irq_data *d)
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{
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unsigned long flags;
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struct pch_lpc *priv = d->domain->host_data;
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raw_spin_lock_irqsave(&priv->lpc_lock, flags);
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writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
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raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
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}
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static void lpc_irq_mask(struct irq_data *d)
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{
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unsigned long flags;
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struct pch_lpc *priv = d->domain->host_data;
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raw_spin_lock_irqsave(&priv->lpc_lock, flags);
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writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
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priv->base + LPC_INT_ENA);
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raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
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}
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static void lpc_irq_unmask(struct irq_data *d)
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{
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unsigned long flags;
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struct pch_lpc *priv = d->domain->host_data;
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raw_spin_lock_irqsave(&priv->lpc_lock, flags);
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writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
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priv->base + LPC_INT_ENA);
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raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
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}
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static int lpc_irq_set_type(struct irq_data *d, unsigned int type)
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{
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u32 val;
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u32 mask = 0x1 << (d->hwirq);
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struct pch_lpc *priv = d->domain->host_data;
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if (!(type & IRQ_TYPE_LEVEL_MASK))
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return 0;
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val = readl(priv->base + LPC_INT_POL);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val |= mask;
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else
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val &= ~mask;
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writel(val, priv->base + LPC_INT_POL);
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return 0;
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}
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static const struct irq_chip pch_lpc_irq_chip = {
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.name = "PCH LPC",
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.irq_mask = lpc_irq_mask,
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.irq_unmask = lpc_irq_unmask,
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.irq_ack = lpc_irq_ack,
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.irq_set_type = lpc_irq_set_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static void lpc_irq_dispatch(struct irq_desc *desc)
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{
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u32 pending, bit;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct pch_lpc *priv = irq_desc_get_handler_data(desc);
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chained_irq_enter(chip, desc);
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pending = readl(priv->base + LPC_INT_ENA);
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pending &= readl(priv->base + LPC_INT_STS);
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if (!pending)
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spurious_interrupt();
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while (pending) {
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bit = __ffs(pending);
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generic_handle_domain_irq(priv->lpc_domain, bit);
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pending &= ~BIT(bit);
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}
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chained_irq_exit(chip, desc);
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}
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static int pch_lpc_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &pch_lpc_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops pch_lpc_domain_ops = {
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.map = pch_lpc_map,
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.translate = irq_domain_translate_twocell,
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};
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static void pch_lpc_reset(struct pch_lpc *priv)
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{
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/* Enable the LPC interrupt, bit31: en bit30: edge */
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writel(LPC_INT_CTL_EN, priv->base + LPC_INT_CTL);
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writel(0, priv->base + LPC_INT_ENA);
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/* Clear all 18-bit interrpt bit */
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writel(GENMASK(17, 0), priv->base + LPC_INT_CLR);
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}
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static int pch_lpc_disabled(struct pch_lpc *priv)
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{
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return (readl(priv->base + LPC_INT_ENA) == 0xffffffff) &&
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(readl(priv->base + LPC_INT_STS) == 0xffffffff);
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}
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static int pch_lpc_suspend(void)
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{
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pch_lpc_priv->saved_reg_ctl = readl(pch_lpc_priv->base + LPC_INT_CTL);
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pch_lpc_priv->saved_reg_ena = readl(pch_lpc_priv->base + LPC_INT_ENA);
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pch_lpc_priv->saved_reg_pol = readl(pch_lpc_priv->base + LPC_INT_POL);
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return 0;
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}
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static void pch_lpc_resume(void)
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{
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writel(pch_lpc_priv->saved_reg_ctl, pch_lpc_priv->base + LPC_INT_CTL);
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writel(pch_lpc_priv->saved_reg_ena, pch_lpc_priv->base + LPC_INT_ENA);
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writel(pch_lpc_priv->saved_reg_pol, pch_lpc_priv->base + LPC_INT_POL);
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}
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static struct syscore_ops pch_lpc_syscore_ops = {
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.suspend = pch_lpc_suspend,
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.resume = pch_lpc_resume,
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};
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int __init pch_lpc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_lpc_pic *acpi_pchlpc)
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{
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int parent_irq;
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struct pch_lpc *priv;
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struct irq_fwspec fwspec;
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struct fwnode_handle *irq_handle;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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raw_spin_lock_init(&priv->lpc_lock);
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priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
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if (!priv->base)
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goto free_priv;
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if (pch_lpc_disabled(priv)) {
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pr_err("Failed to get LPC status\n");
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goto iounmap_base;
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}
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irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
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if (!irq_handle) {
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pr_err("Unable to allocate domain handle\n");
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goto iounmap_base;
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}
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priv->lpc_domain = irq_domain_create_linear(irq_handle, LPC_COUNT,
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&pch_lpc_domain_ops, priv);
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if (!priv->lpc_domain) {
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pr_err("Failed to create IRQ domain\n");
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goto free_irq_handle;
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}
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pch_lpc_reset(priv);
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fwspec.fwnode = parent->fwnode;
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fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
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fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
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fwspec.param_count = 2;
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parent_irq = irq_create_fwspec_mapping(&fwspec);
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irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
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pch_lpc_priv = priv;
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pch_lpc_handle = irq_handle;
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register_syscore_ops(&pch_lpc_syscore_ops);
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return 0;
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free_irq_handle:
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irq_domain_free_fwnode(irq_handle);
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iounmap_base:
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iounmap(priv->base);
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free_priv:
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kfree(priv);
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return -ENOMEM;
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}
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