mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 18:39:59 +00:00
![John Bonesio](/assets/img/avatar_default.png)
This patch creates mpc5200b.dtsi containing the information for the MPC5200b SoC then modifies all of the dts files for MPC5200b based systems to use mpc5200b.dtsi. Signed-off-by: John Bonesio <bones@secretlab.ca> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
218 lines
4.5 KiB
Text
218 lines
4.5 KiB
Text
/*
|
|
* phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
|
|
*
|
|
* Copyright (C) 2006-2009 Pengutronix
|
|
* Sascha Hauer <s.hauer@pengutronix.de>
|
|
* Juergen Beisert <j.beisert@pengutronix.de>
|
|
* Wolfram Sang <w.sang@pengutronix.de>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/include/ "mpc5200b.dtsi"
|
|
|
|
/ {
|
|
model = "phytec,pcm032";
|
|
compatible = "phytec,pcm032";
|
|
|
|
memory {
|
|
reg = <0x00000000 0x08000000>; // 128MB
|
|
};
|
|
|
|
soc5200@f0000000 {
|
|
timer@600 { // General Purpose Timer
|
|
fsl,has-wdt;
|
|
};
|
|
|
|
gpt2: timer@620 { // General Purpose Timer in GPIO mode
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpt3: timer@630 { // General Purpose Timer in GPIO mode
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpt4: timer@640 { // General Purpose Timer in GPIO mode
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpt5: timer@650 { // General Purpose Timer in GPIO mode
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpt6: timer@660 { // General Purpose Timer in GPIO mode
|
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
|
reg = <0x660 0x10>;
|
|
interrupts = <1 15 0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpt7: timer@670 { // General Purpose Timer in GPIO mode
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
psc@2000 { /* PSC1 is ac97 */
|
|
compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
|
|
cell-index = <0>;
|
|
};
|
|
|
|
/* PSC2 port is used by CAN1/2 */
|
|
psc@2200 {
|
|
status = "disabled";
|
|
};
|
|
|
|
psc@2400 { /* PSC3 in UART mode */
|
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
|
};
|
|
|
|
/* PSC4 is ??? */
|
|
psc@2600 {
|
|
status = "disabled";
|
|
};
|
|
|
|
/* PSC5 is ??? */
|
|
psc@2800 {
|
|
status = "disabled";
|
|
};
|
|
|
|
psc@2c00 { /* PSC6 in UART mode */
|
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
|
};
|
|
|
|
ethernet@3000 {
|
|
phy-handle = <&phy0>;
|
|
};
|
|
|
|
mdio@3000 {
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
i2c@3d40 {
|
|
rtc@51 {
|
|
compatible = "nxp,pcf8563";
|
|
reg = <0x51>;
|
|
};
|
|
eeprom@52 {
|
|
compatible = "catalyst,24c32";
|
|
reg = <0x52>;
|
|
pagesize = <32>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pci@f0000d00 {
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
|
0xc000 0 0 2 &mpc5200_pic 1 1 3
|
|
0xc000 0 0 3 &mpc5200_pic 1 2 3
|
|
0xc000 0 0 4 &mpc5200_pic 1 3 3
|
|
|
|
0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
|
|
0xc800 0 0 2 &mpc5200_pic 1 2 3
|
|
0xc800 0 0 3 &mpc5200_pic 1 3 3
|
|
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
|
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
|
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
|
};
|
|
|
|
localbus {
|
|
ranges = <0 0 0xfe000000 0x02000000
|
|
1 0 0xfc000000 0x02000000
|
|
2 0 0xfbe00000 0x00200000
|
|
3 0 0xf9e00000 0x02000000
|
|
4 0 0xf7e00000 0x02000000
|
|
5 0 0xe6000000 0x02000000
|
|
6 0 0xe8000000 0x02000000
|
|
7 0 0xea000000 0x02000000>;
|
|
|
|
flash@0,0 {
|
|
compatible = "cfi-flash";
|
|
reg = <0 0 0x02000000>;
|
|
bank-width = <4>;
|
|
#size-cells = <1>;
|
|
#address-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "ubootl";
|
|
reg = <0x00000000 0x00040000>;
|
|
};
|
|
partition@40000 {
|
|
label = "kernel";
|
|
reg = <0x00040000 0x001c0000>;
|
|
};
|
|
partition@200000 {
|
|
label = "jffs2";
|
|
reg = <0x00200000 0x01d00000>;
|
|
};
|
|
partition@1f00000 {
|
|
label = "uboot";
|
|
reg = <0x01f00000 0x00040000>;
|
|
};
|
|
partition@1f40000 {
|
|
label = "env";
|
|
reg = <0x01f40000 0x00040000>;
|
|
};
|
|
partition@1f80000 {
|
|
label = "oftree";
|
|
reg = <0x01f80000 0x00040000>;
|
|
};
|
|
partition@1fc0000 {
|
|
label = "space";
|
|
reg = <0x01fc0000 0x00040000>;
|
|
};
|
|
};
|
|
|
|
sram@2,0 {
|
|
compatible = "mtd-ram";
|
|
reg = <2 0 0x00200000>;
|
|
bank-width = <2>;
|
|
};
|
|
|
|
/*
|
|
* example snippets for FPGA
|
|
*
|
|
* fpga@3,0 {
|
|
* compatible = "fpga_driver";
|
|
* reg = <3 0 0x02000000>;
|
|
* bank-width = <4>;
|
|
* };
|
|
*
|
|
* fpga@4,0 {
|
|
* compatible = "fpga_driver";
|
|
* reg = <4 0 0x02000000>;
|
|
* bank-width = <4>;
|
|
* };
|
|
*/
|
|
|
|
/*
|
|
* example snippets for free chipselects
|
|
*
|
|
* device@5,0 {
|
|
* compatible = "custom_driver";
|
|
* reg = <5 0 0x02000000>;
|
|
* };
|
|
*
|
|
* device@6,0 {
|
|
* compatible = "custom_driver";
|
|
* reg = <6 0 0x02000000>;
|
|
* };
|
|
*
|
|
* device@7,0 {
|
|
* compatible = "custom_driver";
|
|
* reg = <7 0 0x02000000>;
|
|
* };
|
|
*/
|
|
};
|
|
};
|