Jason Gunthorpe b496df86ac fpga zynq: Check the bitstream for validity ... There is no sense in sending a bitstream we know will not work, and with the variety of options for bitstream generation in Xilinx tools it is not terribly clear what the correct input should be. This is particularly important for Zynq since auto-correction was removed from the driver and the Zynq hardware only accepts a bitstream format that is different from what the Xilinx tools typically produce. Worse, the hardware provides no indication why the bitstream fails, it simply times out if the input is wrong. The best option here is to have the kernel print a message informing the user they are using a malformed bistream and programming failure isn't for any of the myriad of other reasons. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-02-10 15:20:44 +01:00
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altera-fpga2sdram.c	ARM: socfpga: checking the wrong variable	2016-11-17 08:14:55 +01:00
altera-freeze-bridge.c	fpga: add altera freeze bridge support	2016-11-10 17:03:36 +01:00
altera-hps2fpga.c	ARM: socfpga: fpga bridge driver support	2016-11-10 17:03:36 +01:00
fpga-bridge.c	fpga: add fpga bridge framework	2016-11-10 17:03:35 +01:00
fpga-mgr.c	fpga: Clarify how write_init works streaming modes	2016-11-29 15:51:49 -06:00
fpga-region.c	fpga: fpga-region: device tree control for FPGA	2016-11-10 17:03:35 +01:00
Kconfig	fpga: Add COMPILE_TEST to all drivers	2016-11-29 15:51:44 -06:00
Makefile	fpga-manager: Add Socfpga Arria10 support	2016-11-10 17:03:36 +01:00
socfpga-a10.c	fpga: Clarify how write_init works streaming modes	2016-11-29 15:51:49 -06:00
socfpga.c	fpga-mgr: add fpga image information struct	2016-11-10 17:03:35 +01:00
zynq-fpga.c	fpga zynq: Check the bitstream for validity	2017-02-10 15:20:44 +01:00