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4750535bc9
This is a rewrite of the Gemini timer driver in arch/arm/mach-gemini/timer.c trying to do everything the device tree way: - Make every IO-access relative to a base address and dynamic so we can do a dynamic ioremap and get going. - Do not poke around directly in the global syscon registers, access them using the syscon regmap style design pattern for the one register we need to check. - Find register range and interrupt from the device tree. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
277 lines
6.9 KiB
C
277 lines
6.9 KiB
C
/*
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* Gemini timer driver
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* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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*
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* Based on a rewrite of arch/arm/mach-gemini/timer.c:
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* Copyright (C) 2001-2006 Storlink, Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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/*
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* Relevant registers in the global syscon
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*/
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#define GLOBAL_STATUS 0x04
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#define CPU_AHB_RATIO_MASK (0x3 << 18)
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#define CPU_AHB_1_1 (0x0 << 18)
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#define CPU_AHB_3_2 (0x1 << 18)
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#define CPU_AHB_24_13 (0x2 << 18)
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#define CPU_AHB_2_1 (0x3 << 18)
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#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130)
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/*
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* Register definitions for the timers
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*/
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#define TIMER1_COUNT (0x00)
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#define TIMER1_LOAD (0x04)
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#define TIMER1_MATCH1 (0x08)
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#define TIMER1_MATCH2 (0x0c)
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#define TIMER2_COUNT (0x10)
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#define TIMER2_LOAD (0x14)
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#define TIMER2_MATCH1 (0x18)
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#define TIMER2_MATCH2 (0x1c)
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#define TIMER3_COUNT (0x20)
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#define TIMER3_LOAD (0x24)
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#define TIMER3_MATCH1 (0x28)
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#define TIMER3_MATCH2 (0x2c)
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#define TIMER_CR (0x30)
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#define TIMER_INTR_STATE (0x34)
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#define TIMER_INTR_MASK (0x38)
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#define TIMER_1_CR_ENABLE (1 << 0)
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#define TIMER_1_CR_CLOCK (1 << 1)
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#define TIMER_1_CR_INT (1 << 2)
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#define TIMER_2_CR_ENABLE (1 << 3)
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#define TIMER_2_CR_CLOCK (1 << 4)
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#define TIMER_2_CR_INT (1 << 5)
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#define TIMER_3_CR_ENABLE (1 << 6)
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#define TIMER_3_CR_CLOCK (1 << 7)
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#define TIMER_3_CR_INT (1 << 8)
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#define TIMER_1_CR_UPDOWN (1 << 9)
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#define TIMER_2_CR_UPDOWN (1 << 10)
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#define TIMER_3_CR_UPDOWN (1 << 11)
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#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
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TIMER_3_CR_ENABLE | \
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TIMER_3_CR_UPDOWN)
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#define TIMER_1_INT_MATCH1 (1 << 0)
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#define TIMER_1_INT_MATCH2 (1 << 1)
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#define TIMER_1_INT_OVERFLOW (1 << 2)
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#define TIMER_2_INT_MATCH1 (1 << 3)
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#define TIMER_2_INT_MATCH2 (1 << 4)
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#define TIMER_2_INT_OVERFLOW (1 << 5)
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#define TIMER_3_INT_MATCH1 (1 << 6)
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#define TIMER_3_INT_MATCH2 (1 << 7)
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#define TIMER_3_INT_OVERFLOW (1 << 8)
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#define TIMER_INT_ALL_MASK 0x1ff
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static unsigned int tick_rate;
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static void __iomem *base;
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static u64 notrace gemini_read_sched_clock(void)
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{
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return readl(base + TIMER3_COUNT);
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}
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static int gemini_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 cr;
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/* Setup the match register */
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cr = readl(base + TIMER1_COUNT);
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writel(cr + cycles, base + TIMER1_MATCH1);
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if (readl(base + TIMER1_COUNT) - cr > cycles)
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return -ETIME;
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return 0;
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}
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static int gemini_timer_shutdown(struct clock_event_device *evt)
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{
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u32 cr;
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/*
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* Disable also for oneshot: the set_next() call will arm the timer
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* instead.
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*/
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/* Stop timer and interrupt. */
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cr = readl(base + TIMER_CR);
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cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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writel(cr, base + TIMER_CR);
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/* Setup counter start from 0 */
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writel(0, base + TIMER1_COUNT);
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writel(0, base + TIMER1_LOAD);
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/* enable interrupt */
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cr = readl(base + TIMER_INTR_MASK);
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cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
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cr |= TIMER_1_INT_MATCH1;
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writel(cr, base + TIMER_INTR_MASK);
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/* start the timer */
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cr = readl(base + TIMER_CR);
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cr |= TIMER_1_CR_ENABLE;
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writel(cr, base + TIMER_CR);
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return 0;
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}
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static int gemini_timer_set_periodic(struct clock_event_device *evt)
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{
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u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
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u32 cr;
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/* Stop timer and interrupt */
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cr = readl(base + TIMER_CR);
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cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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writel(cr, base + TIMER_CR);
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/* Setup timer to fire at 1/HT intervals. */
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cr = 0xffffffff - (period - 1);
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writel(cr, base + TIMER1_COUNT);
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writel(cr, base + TIMER1_LOAD);
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/* enable interrupt on overflow */
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cr = readl(base + TIMER_INTR_MASK);
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cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
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cr |= TIMER_1_INT_OVERFLOW;
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writel(cr, base + TIMER_INTR_MASK);
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/* Start the timer */
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cr = readl(base + TIMER_CR);
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cr |= TIMER_1_CR_ENABLE;
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cr |= TIMER_1_CR_INT;
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writel(cr, base + TIMER_CR);
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return 0;
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}
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/* Use TIMER1 as clock event */
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static struct clock_event_device gemini_clockevent = {
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.name = "TIMER1",
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/* Reasonably fast and accurate clock event */
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.rating = 300,
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = gemini_timer_set_next_event,
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.set_state_shutdown = gemini_timer_shutdown,
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.set_state_periodic = gemini_timer_set_periodic,
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.set_state_oneshot = gemini_timer_shutdown,
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.tick_resume = gemini_timer_shutdown,
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};
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &gemini_clockevent;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction gemini_timer_irq = {
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.name = "Gemini Timer Tick",
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.flags = IRQF_TIMER,
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.handler = gemini_timer_interrupt,
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};
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static int __init gemini_timer_of_init(struct device_node *np)
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{
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static struct regmap *map;
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int irq;
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int ret;
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u32 val;
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map = syscon_regmap_lookup_by_phandle(np, "syscon");
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if (IS_ERR(map)) {
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pr_err("Can't get regmap for syscon handle");
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return -ENODEV;
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}
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ret = regmap_read(map, GLOBAL_STATUS, &val);
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if (ret) {
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pr_err("Can't read syscon status register");
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return -ENXIO;
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}
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("Can't remap registers");
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return -ENXIO;
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}
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/* IRQ for timer 1 */
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irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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pr_err("Can't parse IRQ");
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return -EINVAL;
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}
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tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
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printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000);
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tick_rate /= 6; /* APB bus run AHB*(1/6) */
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switch (val & CPU_AHB_RATIO_MASK) {
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case CPU_AHB_1_1:
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printk(KERN_CONT "(1/1)\n");
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break;
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case CPU_AHB_3_2:
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printk(KERN_CONT "(3/2)\n");
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break;
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case CPU_AHB_24_13:
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printk(KERN_CONT "(24/13)\n");
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break;
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case CPU_AHB_2_1:
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printk(KERN_CONT "(2/1)\n");
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break;
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}
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/*
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* Reset the interrupt mask and status
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*/
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writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK);
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writel(0, base + TIMER_INTR_STATE);
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writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR);
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled.)
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*/
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writel(0, base + TIMER3_COUNT);
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writel(0, base + TIMER3_LOAD);
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writel(0, base + TIMER3_MATCH1);
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writel(0, base + TIMER3_MATCH2);
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clocksource_mmio_init(base + TIMER3_COUNT,
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"gemini_clocksource", tick_rate,
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300, 32, clocksource_mmio_readl_up);
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sched_clock_register(gemini_read_sched_clock, 32, tick_rate);
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/*
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* Setup clockevent timer (interrupt-driven.)
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*/
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writel(0, base + TIMER1_COUNT);
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writel(0, base + TIMER1_LOAD);
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writel(0, base + TIMER1_MATCH1);
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writel(0, base + TIMER1_MATCH2);
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setup_irq(irq, &gemini_timer_irq);
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gemini_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&gemini_clockevent, tick_rate,
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1, 0xffffffff);
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return 0;
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}
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CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "cortina,gemini-timer",
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gemini_timer_of_init);
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